IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 121

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Control Synchronizer
May 2011 Altera Corporation
Using the Control Synchronizer
The control synchronizer has an address in its Avalon Slave Control port that you can
use to disable or enable the trigger condition. The Control Synchronizer can
optionally be configured before compilation to set this register to the “disabled” value
after every trigger event, this is useful when using the control synchronizer to trigger
only on a single event.
This section provides an example of how to use the Control Synchronizer MegaCore
function. The Control Synchronizer is set to trigger on the changing of the width field
of control data packets. In the following example, the Control Synchronizer is placed
in a system containing a Test Pattern Generator, a Frame Buffer, and a Scaler. The
Control Synchronizer must synchronize a change of the width of the generated video
packets with a change to the Scaler output size, such that the Scaler maintains a
scaling ratio of 1:1 (no scaling). The Frame Buffer is configured to drop and repeat;
this makes it impossible to calculate when packets streamed into the Frame Buffer are
streamed out to the Scaler, which means that the Scaler cannot be configured in
advance of a certain video data packet. The Control Synchronizer solves this problem,
as described in the following scenario.
1. Set up the change of video width as shown in
Figure 5–17. Change of Video Width
Avalon MM
Test Pattern
Generator
changing frame width to 320
Red Line Indicates Control Data Packet and Video Data Packet Pair Number 4 (Width 640)
Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 0 (Width 640)
Control Data packet and Video Data Packet Pair Numbers 1, 2 and 3 are Stored in the Frame Buffer
CPU Writes to
Test Pattern
Generator,
Nios II CPU
Frame
Buffer
Change Scaler Output Size to 320 Width
When a Change in Width is Detected
Synchronizer, Configures it to
CPU Writes to Control
Avalon MM
Master
Synchronizer
Figure
Control
Video and Image Processing Suite User Guide
Avalon MM
5–17.
Scaler
Avalon MM
5–37