IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 182

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–18
Table 6–13. Frame Buffer Signals (Part 2 of 3)
Video and Image Processing Suite User Guide
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
read_master_av_address
read_master_av_burstcount
read_master_av_clock
read_master_av_read
read_master_av_readdata
read_master_av_readdatavalid
read_master_av_reset
read_master_av_waitrequest
reader_control_av_chipselect
reader_control_av_readdata
reader_control_av_write
reader_control_av_writedata
write_master_av_address
write_master_av_burstcount
Signal
Direction
In
Out
Out
In
Out
Out
Out
Out
In
Out
In
In
In
In
In
Out
In
In
Out
Out
din port Avalon-ST valid signal. This signal identifies the cycles
when the port should input data.
dout port Avalon-ST data bus. This bus enables the transfer of
pixel data out of the MegaCore function.
dout port Avalon-ST endofpacket signal. This signal marks the
end of an Avalon-ST packet.
dout port Avalon-ST ready signal. The downstream device
asserts this signal when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks
the start of an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when
the MegaCore function is outputs data.
read_master port Avalon-MM address bus. Specifies a byte
address in the Avalon-MM address space.
read_master port Avalon-MM burstcount signal. Specifies the
number of transfers in each burst.
read_master port The clock signal. The interface operates on the
rising edge of the clock signal.
read_master port Avalon-MM read signal. Asserted to indicate
read requests from the master to the system interconnect fabric.
read_master port Avalon-MM readdata bus. These input lines
carry data for read transfers.
read_master port Avalon-MM readdatavalid signal. The
system interconnect fabric asserts this signal when the requested
read data has arrived.
read_master port reset signal. The interface resets
asynchronously when you assert this signal. You must deassert
this signal synchronously to the rising edge of the clock signal.
read_master port Avalon-MM waitrequest signal. The system
interconnect fabric asserts this signal to cause the master port to
wait.
reader_control slave port Avalon-MM chipselect signal. The
reader_control port ignores all other signals unless you assert
this signal.
reader_control slave port Avalon-MM readdata bus. These
output lines are used for read transfers.
reader_control slave port Avalon-MM write signal. When you
assert this signal, the reader_control port accepts new data
from the writedata bus.
reader_control slave port Avalon-MM writedata bus. These
input lines are used for write transfers.
write_master port Avalon-MM address bus. Specifies a byte
address in the Avalon-MM address space.
write_master port Avalon-MM burstcount signal. Specifies
the number of transfers in each burst.
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Description
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May 2011 Altera Corporation
Chapter 6: Signals
Frame Buffer