IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 200

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

7–8
Table 7–6. Color Space Converter Control Register Map (Part 2 of 2)
Control Synchronizer
Table 7–7. Control Synchronizer Control Register Map (Part 1 of 2)
Video and Image Processing Suite User Guide
2
3
4
5
6
7
8
9
10
11
12
13
0
1
2
3
4
5
6
7
8
9
10
11
12
Address
Address
Coefficient A0
Coefficient B0
Coefficient C0
Coefficient A1
Coefficient B1
Coefficient C1
Coefficient A2
Coefficient B2
Coefficient C2
Summand S0
Summand S1
Summand S2
Control
Status
Interrupt
Disable Trigger
Number of writes
Address 0
Word 0
Address 1
Word 1
Address 2
Word 2
Address 3
Word 3
Register Name
Register(s)
The width of each register of the frame reader is 32 bits. The control data is read once
at the start of each frame. The registers may be safely updated during the processing
of a frame.
register map.
Bit 0 of this register is the Go bit. Setting this bit to 1 causes the Control Synchronizer
MegaCore function to start passing through data. Bit 1 of the Control register is the
interrupt enable. Setting bit 1 to 1, enables the completion of writes interrupt.
Bit 0 of this register is the Status bit. All other bits are unused. Refer to
Slave Interfaces” on page 4–17
Bit 1 of this register is the completion of writes interrupt bit, all other bits are unused.
Writing a 1 to bit 1 resets the completion of writes interrupt.
Setting this register to 1 disables the trigger condition of the control synchronizer. Setting
this register to 0 enables the trigger condition of the control synchronizer. When the
compile time option Require trigger reset via control port is enabled this register value is
automatically set to 1 every time the Control Synchronizer triggers.
This register sets how many write operations, starting with address and word 0, are
written when the control synchronizer triggers.
Address where word 0 should be written on trigger condition.
The word to write to address 0 on trigger condition.
Address where word 1 should be written on trigger condition.
The word to write to address 1 on trigger condition.
Address where word 2 should be written on trigger condition.
The word to write to address 2 on trigger condition.
Address where word 3 should be written on trigger condition.
The word to write to address 3 on trigger condition.
For details, refer to
Table 7–7
describes the Control Synchronizer MegaCore function control
“Color Space Conversion” on page
for full details.
Description
Description
5–33.
Chapter 7: Control Register Maps
May 2011 Altera Corporation
Control Synchronizer
“Avalon-MM