IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 188

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–24
Scaler II
Table 6–18. Scaler II Signals (Part 1 of 2)
Video and Image Processing Suite User Guide
main_clock
main_reset
control_address
control_byteenable
control_read
control_readdata
control_waitrequest
control_write
control_writedata
din_data
din_endofpacket
din_ready
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
Signal
Table 6–18
Direction
In
In
In
In
In
Out
Out
In
In
In
In
Out
In
In
Out
Out
In
Out
shows the input and output signals for the Scaler II MegaCore function.
The main system clock. The MegaCore function operates on the rising edge
of the main_clock signal.
The MegaCore function asynchronously resets when you assert
main_reset. You must deassert main_reset synchronously to the rising
edge of the main_clock_clk signal.
control slave port Avalon-MM address bus. Specifies a word offset into
the slave address space.
control slave port Avalon-MM byteenable bus. Enables specific byte
lane or lanes during transfers. Each bit in byteenable corresponds to a
byte in writedata and readdata. During writes, byteenable specifies
which bytes are being written to; other bytes are ignored by the slave.
During reads, byteenable indicates which bytes the master is reading.
Slaves that simply return readdata with no side effects are free to ignore
byteenable during reads.
control slave port Avalon-MM read signal. When you assert this signal,
the control port outputs new data at readdata.
control slave port Avalon-MM readdata bus. Output lines for read
transfers.
control slave port Avalon-MM waitrequest signal.
control slave port Avalon-MM write signal. When you assert this signal,
the control port accepts new data from the writedata bus.
control slave port Avalon-MM writedata bus. Input lines for write
transfers.
din port Avalon-ST data bus. This bus enables the transfer of pixel data
into the MegaCore function.
din port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates when the MegaCore
function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the cycles when the
port should input data.
dout port Avalon-ST data bus. This bus enables the transfer of pixel data
out of the MegaCore function.
dout port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
dout port Avalon-ST ready signal. The downstream device asserts this
signal when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
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Description
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May 2011 Altera Corporation
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Chapter 6: Signals
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Scaler II