IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 55

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Frame Reader
Table 3–15. Frame Buffer Parameter Settings (Part 2 of 2)
Frame Reader
Table 3–16. Frame Reader Parameter Settings
May 2011 Altera Corporation
Read-only master interface FIFO
depth
Read-only master interface burst
target
Base address of frame buffers
Align read/write bursts with burst
boundaries
Notes to
(1) Locked frame rate conversion cannot be turned on until dropping and repeating are allowed.
(2) Locked frame rate conversion cannot be turned on if the run-time control interface for the writer component has not been enabled.
(3) The Maximum packet length option is not available when the Number of packets buffered per frame is set to 0.
(4) The number of frame buffers and the total memory required at the specified base address is displayed under the base address.
Bits per pixel per color plane
Number of color planes in parallel
Number of color planes in sequence
Maximum image width
Maximum image height
Master port width
Read master FIFO depth
Read master FIFO burst target
Use separate clock for the Avalon-
MM master interface
Table
Parameter
Parameter
3–15:
Table 3–16
(4)
shows the Frame Reader parameters.
16–1024,
Default = 64
2–256, Default = 32
Any 32-bit value,
Default = 0x00000000
On or Off
4–16, Default = 8
1–4, Default = 3
1–3, Default = 3
32–2600, Default =
640
32–2600, Default =
480
8–1024, Default = 64
2–256, Default = 32
On or Off
16–256, Default = 256 The width in bits of the master port
Value
Value
Choose the FIFO depth of the read-only Avalon-MM
interface.
Choose the burst target for the read-only Avalon-MM
interface.
Choose a hexadecimal address for the frame buffers in
external memory.
Turn on to avoid initiating read and write bursts at a
position that would cause the crossing of a memory row
boundary.
The number of bits used per pixel, per color plane
The number color planes transmitted in parallel
The maximum number of color planes transmitted in
sequence
The maximum width of images / video frames
The maximum height of images / video frames
The depth of the read master FIFO
The target burst size of the read master
Use separate clock for the Avalon-MM master interface
Video and Image Processing Suite User Guide
Description
Description
3–17