IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 179

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Deinterlacer II
Table 6–12. Deinterlacer II Signals (Part 2 of 4)
May 2011 Altera Corporation
dout_endofpacket
dout_ready
control_address
control_write
control_writedata
control_read
control_readdata
control_readdatavalid
control_waitrequest
control_byteenable
edi_read_master_address
edi_read_master_read
edi_read_master_burstcount
edi_read_master_readdata
edi_read_master_readdatavalid
edi_read_master_waitrequest
Signal
Direction
Out
In
In
In
In
In
Out
Out
Out
In
Out
Out
Out
In
In
In
dout port Avalon-ST endofpacket signal. This signal
marks the end of an Avalon-ST packet.
dout port Avalon-ST ready signal. The downstream device
asserts this signal when it is able to receive data.
control slave port Avalon-MM address bus. This bus
specifies a word offset into the slave address space.
control slave port Avalon-MM write signal. When you
assert this signal, the control port accepts new data from
the writedata bus.
control slave port Avalon-MM writedata bus. These
input lines are used for write transfers.
control slave port Avalon-MM read signal. When you
assert this signal, the control port outputs new data at
readdata.
control slave port Avalon-MM readdata bus. These
output lines are used for read transfers.
control slave port Avalon-MM readdatavalid bus. The
MegaCore function asserts this signal when the readdata
bus contains valid data in response to the read signal.
control slave port Avalon-MM waitrequest signal.
control slave port Avalon-MM byteenable bus. This bus
enables specific byte lane or lanes during transfers. Each
bit in byteenable corresponds to a byte in writedata
and readdata. During writes, byteenable specifies
which bytes are being written to; the slave ignores other
bytes. During reads, byteenable indicates which bytes
the master is reading. Slaves that simply return readdata
with no side effects are free to ignore byteenable during
reads.
edi_read_master port Avalon-MM address bus. This
bus specifies a byte address in the Avalon-MM address
space.
edi_read_master port Avalon-MM read signal. The
MegaCore function asserts this signal to indicate read
requests from the master to the system interconnect
fabric.
edi_read_master port Avalon-MM burstcount signal.
This signal specifies the number of transfers in each
burst.
edi_read_master port Avalon-MM readdata bus. These
input lines carry data for read transfers.
edi_read_master port Avalon-MM readdatavalid
signal. The system interconnect fabric asserts this signal
when the requested read data has arrived.
edi_read_master port Avalon-MM waitrequest signal.
The system interconnect fabric asserts this signal to cause
the master port to wait.
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Video and Image Processing Suite User Guide
Description
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