IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 150

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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Test Pattern Generator
Video and Image Processing Suite User Guide
The Control Synchronizer MegaCore function ensures that the switch of the video
streams is performed at a safe place in the streams. Performing the switch when the
Alpha Blending Mixer MegaCore function is outputting the start of an image packet,
ensures that the video streams entering the Switch MegaCore function are all on the
same frame. They can then be switched on the next image end-of-packet without
causing a deadlock situation between the Switch and Alpha Blending Mixer.
The following sequence shows an example for layer switching:
1. Switch MegaCore function—Write to the DoutN Output Control registers setting
2. Switch MegaCore function—Enable the function by writing 1 to address 0
3. Switch MegaCore function—Write to the DoutN Output Control registers to
4. Control Synchronizer MegaCore function—Set up the Control Synchronizer to
For information about the compile time parameters for the Switch MegaCore
function, refer to
register map, refer to
to
The Test Pattern Generator MegaCore function can be used to produce a video stream
compliant with the Avalon-ST Video protocol that feeds a video system during its
design cycle. The Test Pattern Generator MegaCore function produces data on request
and consequently permits easier debugging of a video data path without the risks of
overflow or misconfiguration associated with the use of the Clocked Video Input
MegaCore function or of a custom component using a genuine video input.
Table 6–19 on page
up the outputs. For example:
a. Write 1 to address 3
b. Write 2 to address 4
switch the outputs. For example:
a. Write 2 to address 3
b. Write 1 to address 4
write a 1 to the Switch MegaCore function’s Output Switch register on the next
start of an image packet.
Table 3–23 on page
Table 7–21 on page
6–25.
3–23. For information about the run-time control
7–17. For information about the signals, refer
Chapter 5: Functional Descriptions
May 2011 Altera Corporation
Test Pattern Generator