IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 16
![MegaCore Suite W/ 17 DSP Video/image Processing Functions](/photos/24/19/241949/4696158_sml.jpg)
IPS-VIDEO
Manufacturer Part Number
IPS-VIDEO
Description
MegaCore Suite W/ 17 DSP Video/image Processing Functions
Manufacturer
Altera
Type
-r
Specifications of IPS-VIDEO
Software Application
IP CORE, SUITES
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
Suite of IP Functions for Video and Image Processing
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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1–8
Table 1–4. 2D FIR Filter Performance (Part 2 of 2)
Table 1–5. 2D Median Filter Performance
Video and Image Processing Suite User Guide
Sharpening 5×5 symmetric filter, working on 640×480 in 8-bit R’G’B’, using 9 bit coefficients.
Smoothing 7×7 symmetric filter, working on 1,280×720 in 10-bit R’G’B’, using 15 bit coefficients.
Notes to
(1) EP4CGX22BF14C6 devices.
(2) EP4CGX22BF14C6 devices.
3×3 median filtering HDTV 720 pixel monochrome video.
Median filtering 64×64 pixel R’G’B frames using a 3×3 kernel of pixels.
Median filtering 352×288 pixel two color frames using a 5×5 kernel of pixels.
7×7 median filtering 352×288 pixel monochrome video.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Table
2D Median Filter
(2)
(2)
(2)
(2)
(2)
(2)
1–4:
1–5:
(1)
(1)
(1)
(1)
(1)
(1)
Combinational
Combinational
Table 1–5
LUTs/ALUTs
LUTs/ALUTs
10,801
1,894
1,424
3,725
2,648
1,567
1,011
1,529
5,402
2,698
4,863
984
shows the performance figures for the 2D Median Filter.
Registers
Registers
11,192
Logic
2,412
1,804
4,681
3,612
Logic
1,724
1,200
1,674
1,154
5,667
3,832
7,296
230,400
230,400
61,440
61,440
25,600
25,600
28,160
28,160
16,896
16,896
3,072
3,072
Bits
Bits
Memory
Memory
M9K
—
30
—
M9K
8
—
—
—
—
6
2
8
6
M20K
—
—
12
M20K
Chapter 1: About This MegaCore Function Suite
4
—
—
—
—
2
2
4
6
(9×9)
Performance and Resource Utilization
12
—
20
—
(9×9)
DSP Blocks
—
—
—
—
—
—
—
—
DSP Blocks
May 2011 Altera Corporation
(18×18)
(18×18)
—
—
10
6
—
—
—
—
—
—
—
—
197.36
290.36
178.25
239.58
245.64
353.61
272.78
235.07
274.35
216.59
262.61
(MHz)
(MHz)
364.7
f
f
MAX
MAX
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