IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 178

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–14
Table 6–11. Deinterlacer Signals (Part 4 of 4)
Deinterlacer II
Table 6–12. Deinterlacer II Signals (Part 1 of 4)
Video and Image Processing Suite User Guide
write_master_av_writedata
Note to
(1) The signals associated with the write_master and read_master ports are present only when buffering is used.
(2) When you select Motion Adaptive algorithm, two read master interfaces are used.
(3) When you select Motion Adaptive algorithm and turn on Motion bleed, one additional read master (motion_read_master) and one additional
(4) Additional clock and reset signals are available when you turn Use separate clocks for the Avalon-MM master interfaces.
(5) The signals associated with the ma_control port are not present unless you turn on Run-time control of the motion-adaptive blending.
(6) The signals associated with the ker_writer_control port are not present unless you turn on Run-time control for locked frame rate
av_st_clock
av_st_reset
av_mm_clock
av_mm_reset
din_data
din_valid
din_startofpacket
din_endofpacket
din_ready
dout_data
dout_valid
dout_startofpacket
write master (motion_write_master) port are used to read and update motion values.
conversion.
Table
6–11:
Signal
Signal
Table 6–12
function.
shows the input and output signals for the Deinterlacer II MegaCore
Direction
Out
Direction
In
In
In
In
In
In
In
In
Out
Out
Out
Out
write_master port Avalon-MM writedata bus. These
output lines carry data for write transfers. (1),
The main system clock. The MegaCore function operates
on the rising edge of the av_st_clock signal.
The MegaCore function asynchronously resets when you
assert av_st_reset. You must deassert this reset signal
synchronously to the rising edge of the av_st_clock
signal.
Clock for the Avalon-MM interfaces. The interfaces operate
on the rising edge of the av_mm_clock signal.
Reset for the Avalon-MM interfaces. The interfaces
asynchronously resets when you assert av_mm_reset. You
must deassert this reset signal synchronously to the rising
edge of the av_mm_clock signal.
din port Avalon-ST data bus. This bus enables the
transfer of pixel data into the MegaCore function.
din port Avalon-ST valid signal. This signal identifies the
cycles when the port should input data.
din port Avalon-ST startofpacket signal. This signal
marks the start of an Avalon-ST packet.
din port Avalon-ST endofpacket signal. This signal
marks the end of an Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates
when the MegaCore function is ready to receive data.
dout port Avalon-ST data bus. This bus enables the
transfer of pixel data out of the MegaCore function.
dout port Avalon-ST valid signal. The MegaCore function
asserts this signal when it outputs data.
dout port Avalon-ST startofpacket signal. This signal
marks the start of an Avalon-ST packet.
Description
Description
(3)
May 2011 Altera Corporation
Chapter 6: Signals
(3)
(3)
Deinterlacer II