IPS-VIDEO Altera, IPS-VIDEO Datasheet

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... Video and Image Processing Suite User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com UG-VIPSUITE-11.0 Video and Image Processing Suite Document last updated for Altera Complete Design Suite version: Document publication date: User Guide 11.0 May 2011 Single-PDF ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Color Space Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–12 Control Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13 Deinterlacer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–13 Deinterlacer 1–14 Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–14 Frame Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–15 Gamma Corrector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16 Interlacer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–16 Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Scaler 1–17 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–18 May 2011 Altera Corporation Contents Video and Image Processing Suite User Guide ...

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... Structure of Video Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Control Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–7 Use of Control Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Structure of a Control Data Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10 User-Defined and Altera-Reserved Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–11 Video and Image Processing Suite User Guide Contents May 2011 Altera Corporation ...

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... Generator Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–26 Underflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–28 Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29 Active Format Description Inserter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–29 Color Plane Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30 Rearranging Color Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30 Combining Color Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–30 Splitting/Duplicating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–31 Subsampled Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–32 May 2011 Altera Corporation v Video and Image Processing Suite User Guide ...

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... Stall Behavior and Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–69 2D FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–70 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–70 2D Median Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–70 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–70 Alpha Blending Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–71 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–71 Chroma Resampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–72 Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–72 Video and Image Processing Suite User Guide Contents May 2011 Altera Corporation ...

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... Deinterlacer 6–14 Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–17 Frame Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–19 Gamma Corrector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21 Interlacer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–22 Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–23 Scaler 6–24 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–25 Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–26 Chapter 7. Control Register Maps 2D FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1 May 2011 Altera Corporation vii Video and Image Processing Suite User Guide ...

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... Gamma Corrector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–12 Interlacer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–14 Scaler 7–16 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17 Test Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17 Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2 Video and Image Processing Suite User Guide Contents May 2011 Altera Corporation ...

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... This document describes the Altera IP cores that ease the development of video and image processing designs. You can use the following IP cores in a wide variety of image processing and display applications. The Video and Image Processing Suite contains the following MegaCore ■ “2D FIR Filter” ...

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... Table 1–1. Video and Image Processing Suite Release Information Item Version 11.0 (All MegaCore functions) Release Date May 2011 Ordering Code IPS-VIDEO (Video and Image Processing Suite) 00B3 (2D FIR Filter) 00B4 (2D Median Filter) 00B5 (Alpha Blending Mixer) Product IDs 00B1 (Chroma Resampler) 00C8 (Clipper) ...

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... Avalon Memory-Mapped (Avalon-MM) interfaces for run-time control input and connections to external memory blocks ■ Easy-to-use parameter editor for parameterization and hardware generation ■ IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators ■ Support for OpenCore Plus evaluation ■ ...

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... Taking advantage of this characteristic, video transmitted in the Y’CbCr color space often subsamples the color components (Cb and Cr) to save on data bandwidth. Clipper The Clipper MegaCore function clips video streams. You can configure the Clipper at compile time or optionally at run time using an Avalon-MM slave interface. Clocked Video Input The Clocked Video Input MegaCore function converts clocked video formats (such as BT656, BT1120, and DVI) to Avalon-ST Video ...

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... Deinterlacer II require external RAM. The Deinterlacer II provides you the option to detect a 3:2 cadence in the input video sequence and perform a reverse telecine operation for perfect restoration of the original progressive video. May 2011 Altera Corporation 1–5 Video and Image Processing Suite User Guide ...

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... The Switch MegaCore function allows the connection twelve input video streams to twelve output video streams and the run-time reconfiguration of those connections via a control input. Video and Image Processing Suite User Guide Chapter 1: About This MegaCore Function Suite General Description May 2011 Altera Corporation ...

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... MegaCore function during the design cycle to validate a video system without the possible throughput issues associated with a real video input. Design Example A provided design example offers a starting point to quickly understand the Altera video design methodology, enabling you to build full video processing systems on an FPGA. ...

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... DSP Blocks f MAX (MHz) M20K (9×9) (18×18) — — — 245.64 2 — — 353.61 — — — 272.78 2 — — 364.7 — — — 235.07 4 — — 274.35 — — — 216.59 6 — — 262.61 May 2011 Altera Corporation ...

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... Downsampling from 4:4:4 to 4:2:0 with a parallel data interface and run-time control of resolutions up to XGA (1024x768). The parameterization uses anti-aliasing filtering on the horizontal resampling and nearest-neighbor on the vertical. Cyclone IV GX (1) 1,340 Stratix V (2) 840 May 2011 Altera Corporation Memory Logic Registers Bits M9K 1,236 752 ...

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... MAX (MHz) M20K MLAB Bits — — 133.24 3 — 206.57 May 2011 Altera Corporation ...

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... Stratix V (2) 250 Converts Avalon-ST Video to SDI 1080p60 clocked video. Cyclone IV GX (1) 316 Stratix V (2) 241 Notes to Table 1–10: (1) EP4CGX15BF14C6 devices. (2) 5SGXEA7H3F35C3 devices. May 2011 Altera Corporation Memory Logic Registers Bits M9K 461 18,432 3 353 18,432 — 552 43,008 6 426 43,008 — ...

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... DSP Blocks f MAX (MHz) (9×9) (18×18) 6 — 244.56 — 3 351.25 6 — 255.69 — 3 360.62 9 — 247.71 — 9 372.3 3 — 280.11 May 2011 Altera Corporation ...

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... Deinterlacer. Table 1–14. Deinterlacer Performance (Part Combinational Device Family LUTs/ALUTs Deinterlacing 64×64 pixel 8-bit R’G’B’ frames using the bob algorithm with scanline duplication. Cyclone IV GX (1) 525 May 2011 Altera Corporation Memory Logic Registers Bits M9K M20K 359 — ...

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... DSP Blocks f MAX (MHz) M20K (9×9) (18×18) — 4 — 153.23 59 — 2 203.46 — 8 — 153.59 70 — 4 203.67 DSP Blocks f MAX (MHz) (9×9) (18×18) — — — 175.59 May 2011 Altera Corporation ...

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... Reading a video frame through master port width of 128 and outputs them with 1 channel in sequence and 1 channel in parallel, 8-bit data. Cyclone IV GX (1) 1,317 Stratix V (2) 842 Notes to Table 1–16: (1) EP4CGX15BF14C6 devices. (2) 5SGXEA7H3F35C3 devices. May 2011 Altera Corporation Memory Logic Registers Bits M9K M20K 1,487 7,936 — 1,663 7,168 4 ...

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... DSP Blocks f MAX (MHz) (9×9) (18×18) — — — 133.65 0 — — 368.46 — — — 246.67 0 — — 330.14 — — — 242.42 0 — — 333.78 — — — 231.75 May 2011 Altera Corporation ...

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... Scaling 640×480, 8-bit, three color data up to 1,024×768 with linear interpolation. This can be used to convert video graphics array format (VGA - 640×480) to video electronics standards association format (VESA - 1024×768). Cyclone IV GX (1) 977 Stratix V (2) 780 May 2011 Altera Corporation Memory Logic Registers Bits M9K M20K 444 — ...

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... DSP Blocks f MAX (MHz) (9×9) (18×18) — — — 315.06 2 — — 500.00 — — — 315.06 3 — — 490.44 May 2011 Altera Corporation ...

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... Producing a 1920×1080, 10-bit 4:2:2 Y'Cb'Cr' interlaced stream with a parallel data interface. The resolution of the pattern can be changed using the run-time control interface. Cyclone IV GX (1) 338 Stratix V (2) 261 Notes to Table 1–23: (1) EP4CGX15BF14C6 devices. (2) 5SGXEA7H3F35C3 devices. May 2011 Altera Corporation Memory Logic Registers Bits M9K M20K 263 240 3 135 240 — ...

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... Video and Image Processing Suite User Guide Chapter 1: About This MegaCore Function Suite Performance and Resource Utilization May 2011 Altera Corporation ...

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... This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera IP core. The Altera IP Library is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications ...

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... Figure 2–2. Design Flows Note to Figure 2–2: (1) Altera IP cores may or may not support the Qsys and SOPC Builder design flows. The MegaWizard Plug-In Manager flow offers the following advantages: ■ Allows you to parameterize an IP core variant and instantiate into an existing design For some IP cores, this flow generates a complete example design and testbench. ■ ...

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... Tools menu, and follow the prompts in the MegaWizard Plug-In Manager interface to create or edit a custom IP core variation select a specific Altera IP core, click the IP core in the Installed Plug-Ins list in the MegaWizard Plug-In Manager. 4. Specify the parameters on the Parameter Settings pages. For detailed explanations of these parameters, refer to the “ ...

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... For a complete list of models or libraries required to simulate your IP core, refer to the scripts provided with the testbench. For more information about simulating Altera IP cores, refer to Designs in volume 3 of the Quartus II Handbook. Video and Image Processing Suite User Guide ...

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... SOPC Builder defines default connections, which you can modify. The HDL files are ready to be compiled by the Quartus II software to produce output files for programming an Altera device. SOPC Builder generates a simulation testbench module for supported cores that includes basic transactions to validate the HDL files ...

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... In the Quartus II software, click Add/Remove Files in Project and add the .qip file to the project. 7. Compile your design in the Quartus II software. Video and Image Processing Suite User Guide Chapter 2: Getting Started with Altera IP Cores SOPC Builder Design Flow May 2011 Altera Corporation ...

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... During system generation, you can specify whether SOPC Builder generates a simulation model and testbench for the entire system, which you can use to easily simulate your system in any of Altera's supported simulation tools. SOPC Builder also generates a set of ModelSim the testbench and plain-text RTL design files that describe your system in the ModelSim simulation software ...

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... If your system is not part of a Quartus II project and you want to generate synthesis RTL files, turn on Create synthesis RTL files. Video and Image Processing Suite User Guide Chapter 2: Getting Started with Altera IP Cores Qsys System Integration Tool Design Flow section in volume 1 of the Quartus II Handbook and to Quartus ...

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... During system generation, Qsys generates a functional simulation model—or example design that includes a testbench—which you can use to simulate your system in any Altera-supported simulation tool. f For information about the latest Altera-supported simulation tools, refer to the Quartus II Software Release f For general information about simulating Altera IP cores, refer to Designs in volume 3 of the Quartus II Handbook ...

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... The <variation name> prefix is added automatically using the base output file name you specified in the parameter editor. Video and Image Processing Suite User Guide (Part Description TM Plug-In Manager flow, you are prompted to add the .qip file to the current Chapter 2: Getting Started with Altera IP Cores Generated Files May 2011 Altera Corporation ...

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... Settings tab. Figure 3–1. General Page of the Parameter Settings Tab of the 2D FIR Filter Parameter Editor The following sections describe the parameters for each MegaCore function. May 2011 Altera Corporation Cores. The parameter editor allows you to select only legal 3. Parameter Settings Chapter 2, Getting Started ...

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... This can be useful if you require a wider range output on an existing coefficient set. Choose the method for discarding fractional bits resulting from the FIR calculation. Choose the method for signed to unsigned conversion of the FIR results. Chapter 3: Parameter Settings 2D FIR Filter Description (1) (1) (2) (2) May 2011 Altera Corporation ...

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... Number of color 1–3 planes in sequence Filter size 3x3, 5x5 May 2011 Altera Corporation Description Choose the size in pixels of the convolution kernel used in the filtering. Turn on to enable run-time control of the coefficient values. You can choose a predefined set of simple smoothing or simple sharpening coefficients which are used for color model convolution at compile time ...

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... Choose the format/sampling rate format for the output frames. Note that the input and output formats must be different. Choose the algorithm to use in the horizontal direction when re-sampling data to or from 4:4:4. Chapter 3: Parameter Settings Alpha Blending Mixer May 2011 Altera Corporation ...

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... The left and right offset values must be less than or equal to the input image width. (2) The top and bottom offset values must be less than or equal to the input image height. May 2011 Altera Corporation Description Turn on to enable luma-adaptive mode. This mode looks at the luma channel during interpolation and uses this to detect edges ...

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... Choose the required FIFO depth in pixels (limited by the available on-chip memory). Turn on if you want to use the same signal for the input and output video image stream clocks. Turn on to use the optional stop/go control port. Chapter 3: Parameter Settings Clocked Video Input May 2011 Altera Corporation ...

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... Frame / Field 1: Vertical sync Default = 5 May 2011 Altera Corporation Description You can choose from a list of preset conversions or use the other fields in the dialog box to set up custom parameter values. If you click Load values into controls the dialog box is initialized with values for the selected preset conversion ...

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... Specifies whether the synchronization outputs are used Not used ■ Yes - Synchronization outputs, from the Clocked Video Input MegaCore ■ function, (sof, sof_locked) are used Specifies the width of the vid_std bus. Chapter 3: Parameter Settings Clocked Video Output May 2011 Altera Corporation ...

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... Turn on when stream contains two subsampled channels. For other MegaCore functions to be able to treat these channels as two fully sampled channels in sequence, the control packet width must be halved. May 2011 Altera Corporation Value Turn on to enable two pixels on each port. ...

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... Specify the output range minimum value. Specify the number of places to move the binary point. Choose the method of discarding fraction bits resulting from the calculation. Choose the method of signed to unsigned conversion for the results. Chapter 3: Parameter Settings Color Space Converter (CSC) Description May 2011 Altera Corporation ...

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... Editing these values change the actual coefficients and summands and the results values on the General page. Signed coefficients allow negative values; increasing the integer bits increases the magnitude range; and increasing the fraction bits increases the precision. May 2011 Altera Corporation Description Specifies a predefined set of coefficients and summands to use for color model conversion at compile time ...

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... Choose the number of color planes in parallel. Choose a default type for the initial field. The default value is not used if the first field is preceded by an Avalon-ST Control packet. Refer to “Deinterlacing Methods” on page Chapter 3: Parameter Settings Control Synchronizer Description Description 5–40. May 2011 Altera Corporation ...

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... Avalon-MM master ports 16, 32, 64,128, 256 width (3) May 2011 Altera Corporation Value Specifies whether external frame buffers are used buffering mode, data is piped directly from input to output without using external memory. This is possible only with the bob method. Double-buffering routes data via a pair of buffers in external memory ...

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... This MegaCore function does not support interlaced streams where fields are not of the same size (eg, for NTSC, F0 has 244 lines and F1 has 243 lines). Altera recommends that you use the clipper MegaCore function to crop the extra line in F0. (8) The weave and motion-adaptive algorithms stitch together F1 fields with the F0 fields that precede rather than follow them. ...

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... Default = 64 depth Motion Read Master FIFO 2–256, Default = 32 burst target May 2011 Altera Corporation Value Choose the deinterlacing algorithm. For high quality progressive video sequence, choose the Motion Adaptive High Quality option. Turn on to enable run-time control for the cadence detection and reverse pulldown ...

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... Default = 64 Choose the width of the external memory port. 16–1024, Choose the FIFO depth of the write-only Avalon-MM Default = 64 interface. Choose the burst target for the write-only Avalon-MM 2–256, Default = 32 interface. Chapter 3: Parameter Settings Frame Buffer Description May 2011 Altera Corporation ...

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... Maximum image height Master port width Read master FIFO depth Read master FIFO burst target Use separate clock for the Avalon- MM master interface May 2011 Altera Corporation Value 16–1024, Choose the FIFO depth of the read-only Avalon-MM Default = 64 interface. Choose the burst target for the read-only Avalon-MM 2– ...

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... Turn on to propagate interlaced fields unchanged. Turn off to discard interlaced input. Turn on to enable run-time control. Turn on when the content of the control packet specifies which lines to drop when converting a progressive frame into an interlaced field. Chapter 3: Parameter Settings Gamma Corrector Description Description May 2011 Altera Corporation ...

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... Default = 9 horizontal filtering (1) Horizontal Coefficient On or Off Precision: Signed May 2011 Altera Corporation 3–20, and Table 3–21 on page 3–20 Value Turn on to enable run-time control of the image size. When on, the input and output size parameters control the maximum values. When off, the Scaler does not respond to changes of resolution in control packets ...

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... Preview coefficients button to view the current coefficients in a preview window. Turn on to save coefficient memory by using symmetric coefficients. When on and Load coefficient data at run time is also on, coefficient writes beyond phases 2 and 1 are ignored. Chapter 3: Parameter Settings Description Description May 2011 Altera Corporation Scaler ...

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... Algorithm Settings Scaling algorithm Bilinear or Polyphase Always downscale Off pass-through May 2011 Altera Corporation “Choosing and Loading Coefficients” on page Value Choose the number of bits per color plane. Choose the number of color planes sent in parallel. Choose the number of color planes sent in sequence. ...

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... Choose the number of banks of horizontal filter coefficients for polyphase algorithms. Choose the function used to generate the horizontal scaling coefficients. Choose either one for the pre-defined Lanczos functions or choose Custom to use the coefficients saved in a custom coefficients file. Chapter 3: Parameter Settings Scaler II Description May 2011 Altera Corporation ...

Page 61

... Default = 640 Maximum image 32–2600, height Default = 480 May 2011 Altera Corporation Value When a custom function is selected, you can browse for a comma-separated value file containing custom coefficients. Key in the path for the file that contains these custom efficients. Turn on to add extra pipeline stage registers to the data path. ...

Page 62

... Specifies whether to produce a progressive or an interlaced output stream. Choose the standard color bar or a uniform background. When pattern is uniform background, you can specify the individual R’G’B' or Y’ values depending on the currently selected color space. Chapter 3: Parameter Settings Test Pattern Generator May 2011 Altera Corporation ...

Page 63

... Figure 4–1 also have external interfaces that support clocked video standards. These MegaCore functions can connect between the function’s Avalon-ST interfaces and functions using clocked video standards such as BT.656. May 2011 Altera Corporation Avalon ST Connection DDR 2 Memory Function Avalon MM Master to Slave Connection ...

Page 64

... There are also seven packet types reserved for users, and seven packet types reserved for future definition by Altera. The packet type is defined by a 4-bit packet type identifier. This type identifier is the first value of any packet the symbol in the least significant bits of the interface. ...

Page 65

... May 2011 Altera Corporation Figure 4–2 on page 4–3 0 Video data packet User packet types Reserved for future Altera use 13 Ancillary data packet 14 Reserved for future Altera use 15 Control data packet Data of the packet (Split into symbols) X Start Packet type identifier X’s for unused symbols) “ ...

Page 66

... Y' CbCr (4:2:2) where Cb and Cr alternate between consecutive pixels. Figure 4–4. Horizontally Subsampled Y'CbCr Video and Image Processing Suite User Guide Symbol in most significant bits G R Symbol in least significant bits Chapter 4: Interfaces Avalon-ST Video Protocol May 2011 Altera Corporation ...

Page 67

... MegaCore functions of the Video and Image Processing Suite only process video data packets correctly if they use a certain set of color patterns. Chapter 5, Functional Descriptions MegaCore functions use. May 2011 Altera Corporation Plane for even rows Y Plane for odd rows Description Three color planes, B’ ...

Page 68

... Video and Image Processing Suite User Guide Recommended Color Patterns Parallel Sequence May 2011 Altera Corporation Chapter 4: Interfaces Avalon-ST Video Protocol ...

Page 69

... May 2011 Altera Corporation Bits per pixel Video Data, repeating a ...

Page 70

... The fields that follow are 1920 pixels wide and 540 pixels high. The next field is f1 (odd lines) and it is paired with the f0 field that precedes it. Chapter 4: Interfaces Avalon-ST Video Protocol Table 4–4 gives May 2011 Altera Corporation ...

Page 71

... This behavior may not be supported in future releases. Altera recommends for forward compatibility that functions implementing the protocol ensure there is a control data packet immediately preceding each video data packet. ...

Page 72

... X’s for unused symbols) Chapter 4: Interfaces Avalon-ST Video Protocol show examples of control data Symbols in most significant bits Symbols in middle significant bits Symbols in least significant bits End Symbols in most significant bits Symbols in least significant bits End May 2011 Altera Corporation ...

Page 73

... User-Defined and Altera-Reserved Packets The Avalon-ST Video protocol specifies that there are seven packet types reserved for use by users and seven packet types reserved for future use by Altera. The data content of all of these packets is undefined. However the structure must follow the rule that the packets are split into symbols as defined by the number color plane samples sent in one cycle of the color pattern ...

Page 74

... Width 1 1 bits_per_symbol × symbols_per_beat 1 1 Chapter 4: Interfaces Avalon-ST Video Protocol Avalon Table 4–7 does not show Direction Sink to Source Source to Sink Source to Sink Source to Sink Source to Sink May 2011 Altera Corporation ...

Page 75

... This example has one Avalon-ST port named din and one Avalon-ST port named dout. Data flows into the MegaCore function through din, is processed and flows out of the MegaCore function through dout. May 2011 Altera Corporation Parameter Color Pattern 3. 4. ...

Page 76

... Video and Image Processing Suite User Guide Figure 4–12 is: “Functional Descriptions” on page Specifications. All of the Avalon-ST interfaces that the Video and Chapter 4: Interfaces Avalon-ST Video Protocol 5–1. “Latency” on May 2011 Altera Corporation ...

Page 77

... Initially, din_ready is logic '1'. The source driving the input port sets din_valid to logic '1' and puts the blue color value B 2. The source holds din_valid at logic '1' and the green color value G 3. The corresponding red color value R May 2011 Altera Corporation Parameter Color Pattern 2. ...

Page 78

... Video and Image Processing Suite User Guide state that sinks may set ready to logic '0' at any time, for , which is legal because the ready latency of the interface means m+1,n Chapter 4: Interfaces Avalon-ST Video Protocol Avalon May 2011 Altera Corporation ...

Page 79

... If the Go bit is unset while data is being processed, then the MegaCore function stops processing data again at the beginning of the next image data packet and waits until the Go bit is set by external logic. May 2011 Altera Corporation 0x2 0x0 0x0 ...

Page 80

... MegaCore function has started processing the next frame (and therefore setting the Go bit to zero causes it to stop processing at the end of the next frame). Video and Image Processing Suite User Guide Chapter 4: Interfaces Avalon-MM Slave Interfaces ® II processor) to control the gamma corrector May 2011 Altera Corporation ...

Page 81

... Notes to Table (1) The Slave interfaces of the Video and Image Processing MegaCore functions may use either chipselect or read. (2) For slave interfaces that do not have a predefined number of wait cycles to service a read or a write request. (3) For slave interfaces with an interrupt request line. 1 Clock and reset signal types are not included ...

Page 82

... Input 1 Input 32 Output variable Output 1 Output 1 Output variable Output Table 4–11 are read-only and not required by a master interface Chapter 4: Interfaces Avalon-MM Master Interfaces Usage Read-Write (optional) Read-only Read-only Read-Write (optional) Read-write Read-write Read-write Read-only Write-only Write-only May 2011 Altera Corporation ...

Page 83

... Altera recommends that you keep the default values for Number of packets buffered per frame and Maximum packet length, unless you intend to extend the Avalon-ST Video protocol with custom packets. ...

Page 84

... Video and Image Processing Suite User Guide Chapter 4: Interfaces Buffering of Non-Image Data Packets in Memory May 2011 Altera Corporation ...

Page 85

... Result to Output Data Type Conversion After the calculation, the fixed point type of the results must be converted to the integer data type of the output. May 2011 Altera Corporation 5. Functional Descriptions Video and Image Processing Suite User Guide ...

Page 86

... Where this kernel runs over the edge of the input image, zeros are filled in. Video and Image Processing Suite User Guide 5–1. Value and  can be any color plane: , Chapter 5: Functional Descriptions 2D Median Filter α β γ May 2011 Altera Corporation ...

Page 87

... At this stage, the on/off status of each layer is read. A layer can be disabled (0), active and displayed (1) or consumed but not displayed (2). The maximum number of image layers mixed cannot be changed dynamically and must be set in the parameter editor for the Alpha Blending Mixer. May 2011 Altera Corporation Table 5–2. Value 5– ...

Page 88

... Video and Image Processing Suite User Guide (disable/displayed/consumed) 4–17. For details of the control register maps, 7–2. For information about the Avalon-MM interface Table 6–3 on page 6–2. Chapter 5: Functional Descriptions Alpha Blending Mixer layers internal registers May 2011 Altera Corporation ...

Page 89

... For example, if three channels in sequence is selected where dout) ,  and  can be any color plane: , Color Pattern (alpha_in) A single color plane representing the alpha value for each pixel: May 2011 Altera Corporation , where N is the maximum number of layers – 1 ...

Page 90

... It works by simply discarding the Cb and Cr samples that occur on even columns (assuming the first column is numbered 1). This algorithm is very fast and cheap but, due to aliasing effects, it does not produce the best image quality. Video and Image Processing Suite User Guide Sample Chapter 5: Functional Descriptions Chroma Resampler May 2011 Altera Corporation ...

Page 91

... This makes the interpolated chroma samples line up better with edges in the luma channel and is particularly noticeable for bold synthetic edges such as text. May 2011 Altera Corporation (“Choosing and Loading 5–61) that the Scaler MegaCore function uses. Their quantized shows 4:2:2 data at an edge transition ...

Page 92

... For more information about how non-video packets are transferred, refer to Propagation” on page Video and Image Processing Suite User Guide CbCr Color + + Value Y’ Intensity 5–3. Sample 4–11. Chapter 5: Functional Descriptions Chroma Resampler + + Sample – 1]. All output data “Packet May 2011 Altera Corporation ...

Page 93

... Number of bits per color sample selected in the parameter editor. Any combination of one, two, three, or four channels in each of sequence or parallel. For example, if three channels in sequence is selected where , , and  Color Pattern can be any color plane: May 2011 Altera Corporation Table 5–4. Value For 4:2:2 sequential data: ...

Page 94

... The Clocked Video Input MegaCore function converts from clocked video formats (such as BT656, BT1120, and DVI) to Avalon-ST Video. The Clocked Video Input strips the incoming clocked video of horizontal and vertical blanking, leaving only active picture data, and using this data with the horizontal and vertical synchronization information creates the necessary Avalon-ST Video control and active picture packets ...

Page 95

... The Clocked Video Input MegaCore function only reads vid_data when vid_datavalid is high (as in the embedded synchronization format) but it treats each read sample as active picture data. May 2011 Altera Corporation Table 5–6. 8-bit These bits are not inspected by the Clocked Video Input MegaCore [3:0] function ...

Page 96

... When asserted the video active picture period (not horizontal or vertical blanking). When 1, the video horizontal synchronization period. When 1, the video vertical synchronization period. When 1, the video is interlaced and in field 1. When 0, the video is either progressive or interlaced and in field Chapter 5: Functional Descriptions Clocked Video Input Dn+1 Dn+2 May 2011 Altera Corporation ...

Page 97

... Standard—The MegaCore function provides the contents of the vid_std bus via the Standard register. When connected to the rx_std signal of a SDI MegaCore function, for example, these values can be used to report the standard (SD, HD, or 3G) of the incoming video. May 2011 Altera Corporation Field Order F1 first Start, F1, F0, ..., F1, F0, Stop F0 first Start, F0, F1, ...

Page 98

... Stable bit set and interrupt fired 0 —Two of last three lines had the same sample count. 0 End of first field of video. Interlaced bit set—Start of 0 second field of video. 562 End of second field of video. Resolution valid bit set and 562 interrupt fired. May 2011 Altera Corporation ...

Page 99

... An example of how to set up the Clocked Video Input to output an SOF signal aligned to the incoming video synchronization (in embedded synchronization mode) is included in Table Table 5–10. Example of Clocked Video Input To Output an SOF Signal Format SOF Sample Register 720p60 1080i60 NTSC May 2011 Altera Corporation shows an example configuration ...

Page 100

... If the packet is an AFD packet (DID = 0x41, SDID = 0x5), the extractor places the contents of the ancillary packet into the AFD Extractor register map. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Clocked Video Input May 2011 Altera Corporation ...

Page 101

... May 2011 Altera Corporation Register When bit the core discards all packets. Control When bit the core passes through all non- ancillary packets ...

Page 102

... The Clocked Video Output MegaCore function creates a video frame consisting of horizontal and vertical blanking (containing syncs) and areas of active picture (taken from the Avalon-ST Video input). Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Clocked Video Output May 2011 Altera Corporation ...

Page 103

... Chapter 5: Functional Descriptions Clocked Video Output The format of the video frame is shown in on page 5–20 Figure 5–8. Progressive Frame Format May 2011 Altera Corporation Figure 5–8 for interlaced. Horizontal Sync F0 Active Picture Width Vertical Blanking 5–19 for progressive and Figure 5–9 ...

Page 104

... Video and Image Processing Suite User Guide Horizontal Sync F0 Active Picture Width F0 Vertical Blanking F1 Active Picture Width Vertical Blanking (Table 5–6 on page 5–11). Chapter 5: Functional Descriptions Clocked Video Output “Ancillary Data Packets” on May 2011 Altera Corporation ...

Page 105

... Avalon-MM control port. If you turn off Use control port in the parameter editor for the Clocked Video Output, then the output video format always has the format specified in the parameter editor. May 2011 Altera Corporation Description 1 during the horizontal synchronization period. 1 during the vertical synchronization period. ...

Page 106

... Ancillary line H front porch H blanking Video and Image Processing Suite User Guide “Video Formats” on page 5–18. F0 active picture H H back sync Active samples porch Chapter 5: Functional Descriptions Clocked Video Output V front porch V sync V back porch May 2011 Altera Corporation ...

Page 107

... Line line ModeN Valid N/A ModeN Ancillary Line Ancillary line May 2011 Altera Corporation Figure 5–10 relates to the register map. Description The zeroth bit of this register is the Interlaced bit: Set to 0 for progressive. Bit 1 of this register is the sequential output ■ ...

Page 108

... Video and Image Processing Suite User Guide “Video Formats” on page 5–18. F0 active picture F1 active picture H back Active samples porch Chapter 5: Functional Descriptions Clocked Video Output F0 V front porch F0 V sync F0 V back porch V front porch V sync V back porch May 2011 Altera Corporation ...

Page 109

... F falling edge line ModeN Valid N/A ModeN Ancillary Line Ancillary line ModeN F0 Ancillary Line F0 ancillary line May 2011 Altera Corporation Figure 5–11 relates to the register map. Description The zeroth bit of this register is the Interlaced bit: Set to 0 for interlaced. ■ Bit 1 of this register is the sequential output control bit (only if the Allow ■ ...

Page 110

... Control register. When Genlock functionality is enabled the Clocked Video Output MegaCore does not synchronize itself to the incoming Avalon-ST Video. Altera recommends that you disable Genlock functionality before changing output mode and then only enable it again when the status update interrupt has fired, indicating that the mode change has occurred ...

Page 111

... Vcoclk Divider register), the Clocked Video Output does not alter the output video. If your PFD clock tracking has a delay associated with it, Altera recommends that even if the vcoclk_div signal is not being used, the Vcoclk Divider register should be set to a threshold value e ...

Page 112

... In addition to the underflow bit, the current level of the FIFO can be read from the Used Words register. Video and Image Processing Suite User Guide Phase Detector Charge Divider + Pump - Feedback Divider sof sof_locked Chapter 5: Functional Descriptions Clocked Video Output 27 MHz VCXO vid_clk Clocked SDI Video TX Output May 2011 Altera Corporation ...

Page 113

... Table 5–15. AFD Inserter Register Map Address May 2011 Altera Corporation Register When bit the core discards all packets. Control When bit the core passes through all non- ancillary packets. Reserved. Reserved. AFD Bits 0-3 contain the active format description code. AR Bit 0 contains the aspect ratio code ...

Page 114

... When the color pattern of a video data packet changes from the input to the output side of a block, the color sequencer adds padding to the end of non-video data packets with extra data. Altera recommends that when you define a packet type where the length is variable and meaningful, you send the length at the start of the packet. ...

Page 115

... This allows for splitting of video data packets, duplication of video data packets mix of splitting and duplication. The output color patterns are independent of each other, so the arrangement of one output stream's color pattern places no limitation on the arrangement of the other output stream's color pattern. May 2011 Altera Corporation ...

Page 116

... Chapter 5: Functional Descriptions Color Plane Sequencer R G Color pattern of a video data packet on output stream 0 2 color plane samples in parallel G B Color pattern of a video data packet on output stream 1 2 color plane samples in sequence May 2011 Altera Corporation ...

Page 117

... Conversions between color spaces are achieved by providing an array of nine coefficients and three summands that relate the color spaces. These can be set at compile time run time using the Avalon-MM slave interface. May 2011 Altera Corporation Table Value Read from control packets at run time. ...

Page 118

... Predefined conversions are based on the input bits per pixel per color plane. If using different input and output bits per pixel per color plane, the results should be scaled by the correct number of binary places to compensate. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Color Space Converter May 2011 Altera Corporation ...

Page 119

... May 2011 Altera Corporation 5–35 Video and Image Processing Suite User Guide ...

Page 120

... Read from control packets at run time. Either. Number of bits per color sample selected in the parameter editor. For color planes in sequence: (1) For color planes in parallel: 5–17: “Avalon-ST Video Protocol” on page Chapter 5: Functional Descriptions Control Synchronizer Value 4–2. May 2011 Altera Corporation ...

Page 121

... Red Line Indicates Control Data Packet and Video Data Packet Pair Number 4 (Width 640) Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 0 (Width 640) Control Data packet and Video Data Packet Pair Numbers 1, 2 and 3 are Stored in the Frame Buffer May 2011 Altera Corporation Avalon MM Frame ...

Page 122

... Control Buffer Synchronizer Avalon MM Nios II CPU Control Synchronizer Writes the Data to the Specified Addresses. This Configures the Scaler to an Output Width of 320 Avalon MM Master Frame Control Buffer Synchronizer Avalon MM Nios II CPU Control Synchronizer Avalon MM Scaler Avalon MM Scaler May 2011 Altera Corporation ...

Page 123

... Producing one output frame for each input field should give smoother motion but may also introduce visual artefacts on scrolling text or slow moving objects when using the bob or motion adaptive algorithm. May 2011 Altera Corporation Frame Generator Buffer Nios II CPU ...

Page 124

... Motion-adaptive Video and Image Processing Suite User Guide “Control Data Packets” on page Memory Memory Writer Reader (write_master) Arbitration Logic DDR2 SDRAM Chapter 5: Functional Descriptions Deinterlacer 4–7.) When input Deinterlacing Algorithm Avalon-ST Output (dout) Avalon-MM Master (read_master) May 2011 Altera Corporation ...

Page 125

... The Deinterlacer does not support interlaced streams where F0 fields are one line higher than F1 fields in most of its parameterizations. (Bob with one output frame for each input frame is the only exception.) Altera recommends using the Clipper MegaCore function to feed the Deinterlacer with an interlaced video stream that it can support ...

Page 126

... This action reduces unpleasant flickering artefacts but increases the memory usage and memory bandwidth requirements. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions (Figure 5–22 Current Field (C) Figure Previous Frame Current Frame , Deinterlacer X 5–23shows the May 2011 Altera Corporation ...

Page 127

... When you select double-buffering, external RAM uses two frame buffers. Input pixels flow through the input port and into one buffer while pixels are read from the other buffer, processed and output. May 2011 Altera Corporation Upper Pixel + Lower Pixel Output Pixel = M . ...

Page 128

... Turning on this option may have a negative impact on memory usage but increases memory efficiency. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Deinterlacer May 2011 Altera Corporation ...

Page 129

... When the bob algorithm is used and synchronization is done on a specific field (input frame rate = output frame rate), the field that is constantly unused is always discarded. The other field is used to build a progressive frame, unless it is dropped by the triple-buffering algorithm. May 2011 Altera Corporation 5–45 Table 7–8 on Video and Image Processing Suite User Guide ...

Page 130

... Video and Image Processing Suite User Guide “Buffering of Non-Image Data Packets in 4–21. 5–19. Value Chapter 5: Functional Descriptions Deinterlacer Table 4–4 on page 4–8.) α β γ and , May 2011 Altera Corporation ...

Page 131

... Additionally, the Deinterlacer II does not use external memory when propagating progressive frames. ■ The Deinterlacer II does not provide double and triple-buffering, and does not support the user-defined frame rate conversion feature offered in the Deinterlacer. May 2011 Altera Corporation Deinterlacer MegaCore function. The Deinterlacer II does not Memory Memory ...

Page 132

... The Frame Buffer is built with two basic blocks: a writer which stores input pixels in memory and a reader which retrieves video frames from the memory and outputs them. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Frame Buffer MegaCore function into the designs. Frame Buffer May 2011 Altera Corporation ...

Page 133

... If dropping frames is not allowed, the writer component stalls until the reader component has finished its frame and replaced the spare buffer with a dirty buffer. May 2011 Altera Corporation Memory Writer ...

Page 134

... For more information, refer to Video and Image Processing Suite User Guide describes the control register maps for the Frame Buffer “Control Data Packets” on page Chapter 5: Functional Descriptions Frame Buffer 4–7. May 2011 Altera Corporation ...

Page 135

... The Frame Reader has an Avalon-ST source on which it streams video data using the Avalon-ST Video protocol. The Frame Reader also has an Avalon slave port, which provides the MegaCore function with configuration data. May 2011 Altera Corporation “Buffering of Non-Image Data Packets in Memory” on page 5–51. ...

Page 136

... Frame Reader MegaCore, which is configured for: ■ 8 bits per pixel per color plane ■ 3 color planes in parallel ■ Master port width 64 Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Frame Reader May 2011 Altera Corporation ...

Page 137

... The Avalon-ST Video parameters for the Frame Reader MegaCore function are shown in Table 5–21. Table 5–21. Avalon-ST Video Parameters (Part Parameter Frame Width Frame Height Interlaced / Progressive May 2011 Altera Corporation Table 5–21 ...

Page 138

... N bits wide are the look-up values for the gamma correction function. Image Table 5–22. Value Chapter 5: Functional Descriptions Gamma Corrector Value Table 7–14 on page 7–13, 7–13. For information about the 6–21. α β May 2011 Altera Corporation γ ...

Page 139

... Video and Image Processing Suite, refer to page 4–17. For details of the register map for the Scaler MegaCore function, refer to Table 7–18 on page May 2011 Altera Corporation Table 7–17 on page 7–14 4–8. 5–23. The Interlacer does not support vertically subsampled video Value “ ...

Page 140

... Video and Image Processing Suite User Guide and h respectively. The width and height of the output image in in and the function that returns an intensity value for a given out out /w , (j+0. out in out × )/(2 × × out Chapter 5: Functional Descriptions × )/(2 × out May 2011 Altera Corporation Scaler ...

Page 141

... B and B fh Their values can be calculated as: where % is the modulus operator and max( function that returns the maximum of two values. May 2011 Altera Corporation )/w in out )/h in out û, in û ...

Page 142

... B        – err err + Chapter 5: Functional Descriptions err –     err    fv err + – + –    err   err May 2011 Altera Corporation Scaler  err j ...

Page 143

... It is equal to the sum of integer bits and fraction bits for the vertical coefficients, plus one if coefficients are signed. May 2011 Altera Corporation shows the flow of data through an instance of the scaler in Line Buffer Delay ...

Page 144

... For each coefficient type, the Quartus II software maps h Chapter 5: Functional Descriptions and P are the user-defined v h the number of horizontal h , and the bit width of the horizontal Table 3–19 on page 3–19. bits wide and P × × Table 7–18 on May 2011 Altera Corporation Scaler ×C v bits ...

Page 145

... When the coefficients are read at run time, they are checked once per frame and double-buffered so that they can be updated as the MegaCore function processes active data without causing corruption. Figure 5–28 on page 5–62 (usually referred to as Lanczos 2) would be sampled for a 4-tap vertical filter. May 2011 Altera Corporation vertical taps and N horizontal taps, the filter – ...

Page 146

... N LanczosN x    ------------------- - ---------------------------- =     0 increments towards tap 2. The filtering coefficients v 1 Chapter 5: Functional Descriptions Scaler      phase(0) phase(P /2) v phase(P − May 2011 Altera Corporation ...

Page 147

... Coefficients for the bicubic algorithm are calculated using Catmull-Rom splines to interpolate between values in tap 1 and tap 2. 1 Altera recommends that you use the Scaler II MegaCore function if your designs require custom coefficients. f For more information about the mathematics for Catmull-Rom splines refer to E Catmull and R Rom. A class of local interpolating splines. Computer Aided Geometric Design, pages 317– ...

Page 148

... MegaCore function. However, the Scaler II resizes video streams    % phase = ------------------------------------------------------- - i w out    % phase = ---------------------------------------------------- - j h out Chapter 5: Functional Descriptions Scaler II Precision Coefficients Lanczos-2, or Bicubic Lanczos-2 Lanczos-1 α β γ  P  out h  P  out v May 2011 Altera Corporation ...

Page 149

... Figure 5–29 shows the system configuration used to achieve this. Figure 5–29. Example of a layer Switching System Switch MegaCore Function Video Stream 1 Video Stream 2 Avalon-MM Slave Control May 2011 Altera Corporation Background Layer Alpha Blending Layer 1 Mixer MegaCore Function Layer 2 5–65 Figure 5– ...

Page 150

... MegaCore function custom component using a genuine video input. Video and Image Processing Suite User Guide Table 3–23 on page 3–23. For information about the run-time control Table 7–21 on page 7–17. For information about the signals, refer 6–25. Chapter 5: Functional Descriptions Test Pattern Generator May 2011 Altera Corporation ...

Page 151

... Cb and Cr components when the output is in the Y’CbCr color space, the black borders at the left and right are two pixels wide. Similarly, the top and bottom borders are two pixels wide when the output is vertically subsampled. May 2011 Altera Corporation Table 5–26 (assuming 8 bits per color R’ ...

Page 152

... The Test Pattern Generator MegaCore function can output streams of pixel data of the types shown in Video and Image Processing Suite User Guide Table 7–22 on page 7–18. is slightly modified: //Copies control to internal register Table 5–27. Chapter 5: Functional Descriptions Test Pattern Generator May 2011 Altera Corporation ...

Page 153

... The Test Pattern Generator cannot produce interlaced streams of pixel data with an odd frame height. To create interlaced video streams where F0 fields are one line higher than F1 fields, Altera recommends feeding Test Pattern Generator progressive video output into the Interlacer MegaCore function. Table 5–27. Test Pattern Generator Avalon-ST Video Protocol Parameters Parameter Width selected in the parameter editor ...

Page 154

... An error condition occurs if an endofpacket signal is received too early or too late for the compile-time-configured frame size. In either case, the 2D FIR Filter always creates output video packets of the configured size. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Stall Behavior and Error Recovery May 2011 Altera Corporation ...

Page 155

... A large number of samples may have to be discarded during the operation and backpressure can be applied for a long time on most input layers. Consequently, this error recovery mechanism could trigger an overflow at the input of the system. May 2011 Altera Corporation 5–71 Video and Image Processing Suite User Guide ...

Page 156

... Once its input FIFO is full, the stall behavior of the Clocked Video Output MegaCore function is dictated by the outgoing video. During horizontal and vertical blanking periods it stalls and does not take in any more video data. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Stall Behavior and Error Recovery May 2011 Altera Corporation ...

Page 157

... MegaCore functions. If the slaves do not provide a “wait request” signal, the stall lasts for no more than 50 clock cycles. Otherwise the stall is of unknown length. 1 Clipper and scaler use the wait_request signal. May 2011 Altera Corporation 5–73 Video and Image Processing Suite User Guide ...

Page 158

... If an early endofpacket signal is received when the Deinterlacer is configured for no buffering, the MegaCore function interrupts its processing within one or two lines sending undefined pixels, before propagating the endofpacket signal. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Stall Behavior and Error Recovery May 2011 Altera Corporation ...

Page 159

... For this MegaCore function there is no such condition as an early or late endofpacket. Any mismatch of the endofpacket signal and the frame size is propagated unchanged to the next MegaCore function. May 2011 Altera Corporation 5–75 Video and Image Processing Suite User Guide ...

Page 160

... In other modes, it adds a maximum of 60 cycles delay. Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Stall Behavior and Error Recovery vertical taps, N – 1 lines of input are read into line v v May 2011 Altera Corporation ...

Page 161

... On receiving an early endofpacket signal, the Scaler stalls its input but continues writing data until it has sent an entire frame does not receive an endofpacket signal at the end of a frame, the Scaler discards data until the end-of-packet is found. May 2011 Altera Corporation vertical taps, N – 1 lines of input are read into line ...

Page 162

... Chroma Resampler Input format: 4:2:0; Output format: 4:4:4 or 4:2:2 Clipper All modes Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Latency Latency (Note 1) (N–1) lines +O (cycles) (N–1) lines +O (cycles) O (cycles) O (cycles) 1 line + O (cycles) O (cycles) May 2011 Altera Corporation ...

Page 163

... It is assumed that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high). (2) Add 1 cycle if Allow color planes in sequence input is turned on. (3) Minimum latency case when video input and output rates are synchronized. May 2011 Altera Corporation 5–79 Latency ...

Page 164

... After the initial buffering phase, the latency from field input to frame output (assuming the output frame rate is the same as the input field rate) is one field + O (lines). Video and Image Processing Suite User Guide Chapter 5: Functional Descriptions Latency May 2011 Altera Corporation ...

Page 165

... Out dout_startofpacket Out dout_valid May 2011 Altera Corporation Table 6–20 list the input and output signals for the Video and Image The main system clock. The MegaCore function operates on the rising edge of the clock signal. The MegaCore function asynchronously resets when you assert reset. You must deassert reset synchronously to the rising edge of the clock signal ...

Page 166

... Avalon-ST data bus for layer N. This bus enables the In transfer of pixel data into the MegaCore function. alpha_in_N port Avalon-ST endofpacket signal. This signal marks the In end of an Avalon-ST packet. Chapter 6: Signals 2D Median Filter Description (1) (1) May 2011 Altera Corporation ...

Page 167

... Avalon-MM address bus. Specifies a word offset In into the slave address space. control slave port Avalon-MM chipselect signal. The control port In ignores all other signals unless you assert this signal. control slave port Avalon-MM readdata bus. These output lines are Out used for read transfers ...

Page 168

... Avalon-MM address bus. Specifies a word offset into the slave address space. (1) control slave port Avalon-MM chipselect signal. The control port ignores all other signals unless you assert this signal. control slave port Avalon-MM readdata bus. These output lines are used for read transfers ...

Page 169

... In av_read Out av_readdata May 2011 Altera Corporation control slave port Avalon-MM waitrequest signal. control slave port Avalon-MM write signal. When you assert this signal, the control port accepts new data from the writedata bus. control slave port Avalon-MM writedata bus. These input lines are used for write transfers ...

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... Clocked video locked signal. Assert this signal when a stable video stream is present on the input. Deassert this signal when the video stream is removed. Chapter 6: Signals Clocked Video Input (1) (1) May 2011 Altera Corporation ...

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... In is_valid In sof May 2011 Altera Corporation Description Video Standard bus. Can be connected to the rx_std signal of the SDI MegaCore function (or any other interface) to read from the Standard register. (Separate Synchronization Mode Only.) Clocked video vertical synchronization signal. Assert this signal during the vertical synchronization period of the video stream ...

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... Synchronization Mode Only.) Clocked video vertical blanking signal. This signal is asserted during the vertical blanking period of the video stream. (Separate Synchronization Mode Only.) Clocked video vertical synchronization signal. This signal is asserted during the vertical synchronization period of the video stream. Chapter 6: Signals Clocked Video Output (1) May 2011 Altera Corporation ...

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... In din_data In din_endofpacket May 2011 Altera Corporation Description The main system clock. The MegaCore function operates on the rising edge of the clock signal. The MegaCore function asynchronously resets when you assert reset. You must deassert reset synchronously to the rising edge of the clock signal. ...

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... MegaCore function. dout port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet. dout port Avalon-ST ready signal. The downstream device asserts this signal when it is able to receive data. Chapter 6: Signals Control Synchronizer May 2011 Altera Corporation ...

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... Signal clock reset din_data din_endofpacket din_ready May 2011 Altera Corporation Description dout port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. dout port Avalon-ST valid signal. This signal is asserted when the MegaCore function is outputs data. slave port Avalon-MM address. Specifies a word offset into the slave address space ...

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... Avalon-MM address bus. This bus In specifies a word offset into the slave address space. ma_control slave port Avalon-MM chipselect signal. In The ma_control port ignores all other signals unless you assert this signal. (5) ma_control slave port Avalon-MM readdata bus. The ...

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... May 2011 Altera Corporation Direction Description ma_control slave port Avalon-MM writedata bus. The In MegaCore function uses these input lines for write transfers. (5) read_master_N port Avalon-MM address bus. This bus Out specifies a byte address in the Avalon-MM address space. ...

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... MegaCore function. dout port Avalon-ST valid signal. The MegaCore function Out asserts this signal when it outputs data. dout port Avalon-ST startofpacket signal. This signal Out marks the start of an Avalon-ST packet. Chapter 6: Signals Deinterlacer II (3) (3) (3) May 2011 Altera Corporation ...

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... May 2011 Altera Corporation Direction Description dout port Avalon-ST endofpacket signal. This signal Out marks the end of an Avalon-ST packet. dout port Avalon-ST ready signal. The downstream device In asserts this signal when it is able to receive data. ...

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... Avalon-MM burstcount signal. This Out signal specifies the number of transfers in each burst. write_master port Avalon-MM writedata bus. These Out output lines carry data for write transfers. Chapter 6: Signals Deinterlacer II (1) (1) (1) (2) (1) (2) (1) (2) May 2011 Altera Corporation ...

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... Table 6–13. Frame Buffer Signals (Part Signal clock reset din_data din_endofpacket din_ready din_startofpacket May 2011 Altera Corporation Direction write_master port Avalon-MM waitrequest signal. The In system interconnect fabric asserts this signal to cause the master port to wait. motion_write_master port Avalon-MM address bus. Out This bus specifies a byte address in the Avalon-MM address space ...

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... Avalon-MM waitrequest signal. The system In interconnect fabric asserts this signal to cause the master port to wait. (2) reader_control slave port Avalon-MM chipselect signal. The In reader_control port ignores all other signals unless you assert this signal. (2) reader_control slave port Avalon-MM readdata bus. These Out output lines are used for read transfers ...

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... Avalon-MM writedata bus. These output Out lines carry data for write transfers. writer_control slave port Avalon-MM chipselect signal. The In writer_control port ignores all other signals unless you assert this signal. (3) writer_control slave port Avalon-MM readdata bus ...

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... You must deassert this signal synchronously to the rising edge of the clock signal. master port The clock signal. The interface operates on In the rising edge of the clock signal. Chapter 6: Signals Frame Reader Description May 2011 Altera Corporation ...

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... Avalon-MM address. Specifies a word offset into the slave address space. gamma_lut slave port Avalon-MM chipselect signal. The gamma_lut port ignores all other signals unless you assert this signal. gamma_lut slave port Avalon-MM readdata bus. These output lines are used for read transfers ...

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... Avalon-MM address bus. Specifies a word offset into the slave address space. (1) control slave port Avalon-MM chipselect signal. The control port ignores all other signals unless you assert this signal. control slave port Avalon-MM readdata bus. These output lines are used for read transfers ...

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... Avalon-MM address bus. Specifies a word offset into the slave address space. (1) control slave port Avalon-MM chipselect signal. The control port ignores all other signals unless you assert this signal. control slave port Avalon-MM readdata bus. These output lines are used for read transfers ...

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... Avalon-ST endofpacket signal. This signal marks the end of an Avalon-ST packet. dout port Avalon-ST ready signal. The downstream device asserts this signal when it is able to receive data. dout port Avalon-ST startofpacket signal. This signal marks the start of an Avalon-ST packet. Chapter 6: Signals Scaler II (1) (1) (1) May 2011 Altera Corporation ...

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... May 2011 Altera Corporation dout port Avalon-ST valid signal. This signal is asserted when the MegaCore function outputs data. Direction The main system clock. The MegaCore function operates on the rising In edge of the clock signal. The MegaCore function asynchronously resets when you assert reset. ...

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... Avalon-MM address bus. Specifies a word offset into the slave address space. (1) control slave port Avalon-MM chipselect signal. The control port ignores all other signals unless you assert this signal. control slave port Avalon-MM readdata bus. These output lines are used for read transfers ...

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... Out dout_valid Note to Table 6–20 (1) These ports are present only if you turn on Run-time control of image size. May 2011 Altera Corporation Description dout port Avalon-ST valid signal. This signal is asserted when the MegaCore function outputs data. 6–27 Video and Image Processing Suite User Guide ...

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... Video and Image Processing Suite User Guide Chapter 6: Signals Test Pattern Generator May 2011 Altera Corporation ...

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... Coefficient 2 The coefficient at position: ■ n Coefficient n ■ May 2011 Altera Corporation 7. Control Register Maps “Avalon-MM Slave Interfaces” on page Description “Avalon-MM Slave Interfaces” on page 4–17 for full details. Row (where 0 is the top row of the kernel) is the integer value via the truncation of (n– ...

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... Description for full details. for full details. describes the Clipper MegaCore function control register map. Description for full details. for full details. Chapter 7: Control Register Maps Alpha Blending Mixer “Avalon-MM Slave (1) (1) “Avalon-MM Slave Interfaces” on (1) May 2011 Altera Corporation ...

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... Notes to Table 7–3: (1) The left and right offset values must be less than or equal to the input image width. (2) The top and bottom offset values must be less than or equal to the input image height. May 2011 Altera Corporation Description (1) (2) (2) Video and Image Processing Suite User Guide ...

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... The detected sample count of the video streams excluding blanking. The detected line count of the video streams F0 field excluding blanking. The detected line count of the video streams F1 field excluding blanking. Chapter 7: Control Register Maps Clocked Video Input “Control Port” for full details. May 2011 Altera Corporation ...

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... Register 0 Control 1 Status May 2011 Altera Corporation Description The detected sample count of the video streams including blanking. The detected line count of the video streams F0 field including blanking. The detected line count of the video streams F1 field including blanking. The contents of the vid_std signal. ...

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... Video mode 1 field rising edge. Specifies the line number given to the end of Field 0 and the start of Field 1. Video mode 1 field falling edge. Specifies the line number given to the end of Field 0 and the start of Field 1. Chapter 7: Control Register Maps Clocked Video Output May 2011 Altera Corporation ...

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... Bit 0 of this register is the Status bit, all other bits are unused. Refer to 1 Status Slave Interfaces” on page 4–17 May 2011 Altera Corporation Description The value output on the vid_std signal. Start of frame sample register. The sample and subsample upon which the SOF occurs (and the vid_sof signal triggers): Bits 0– ...

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... The word to write to address 3 on trigger condition. Word 3 Video and Image Processing Suite User Guide Description “Color Space Conversion” on page describes the Control Synchronizer MegaCore function control Description for full details. Chapter 7: Control Register Maps Control Synchronizer 5–33. “Avalon-MM May 2011 Altera Corporation ...