IPS-VIDEO Altera, IPS-VIDEO Datasheet - Page 173

• Manufacturer Part Number: IPS-VIDEO
• Description: MegaCore Suite W/ 17 DSP Video/image Processing Functions
• Manufacturer: Altera
• Type: -r

Specifications of IPS-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: Suite of IP Functions for Video and Image Processing
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Color Plane Sequencer
Color Plane Sequencer
Table 6–8. Color Plane Sequencer Signals
Color Space Converter
Table 6–9. Color Space Converter Signals (Part 1 of 2)
May 2011 Altera Corporation
clock
reset
dinN_data
dinN_endofpacket
dinN_ready
dinN_startofpacket
dinN_valid
doutN_data
doutN_endofpacket
doutN_ready
doutN_startofpacket
doutN_valid
clock
reset
din_data
din_endofpacket
Signal
Signal
Table 6–8
MegaCore function.
Table 6–9
MegaCore function.
Direction
In
In
In
In
Direction
In
In
In
In
Out
In
In
Out
Out
In
Out
Out
shows the input and output signals for the Color Plane Sequencer
shows the input and output signals for the Color Space Converter
The main system clock. The MegaCore function operates on the rising edge of the
clock signal.
The MegaCore function asynchronously resets when you assert reset. You must
deassert reset synchronously to the rising edge of the clock signal.
din port Avalon-ST data bus. This bus enables the transfer of pixel data into the
MegaCore function.
din port Avalon-ST endofpacket signal. This signal marks the end of an Avalon-
ST packet.
The main system clock. The MegaCore function operates on the rising edge of
the clock signal.
The MegaCore function asynchronously resets when you assert reset. You
must deassert reset synchronously to the rising edge of the clock signal.
dinN port Avalon-ST data bus. This bus enables the transfer of pixel data into
the MegaCore function.
dinN port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
dinN port Avalon-ST ready signal. This signal indicates when the MegaCore
function is ready to receive data.
dinN port Avalon-ST startofpacket signal. This signal marks the start of an
Avalon-ST packet.
dinN port Avalon-ST valid signal. This signal identifies the cycles when the
port should input data.
doutN port Avalon-ST data bus. This bus enables the transfer of pixel data out
of the MegaCore function.
doutN port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
doutN port Avalon-ST ready signal. The downstream device asserts this signal
when it is able to receive data.
doutN port Avalon-ST startofpacket signal. This signal marks the start of an
Avalon-ST packet.
doutN port Avalon-ST valid signal. This signal is asserted when the MegaCore
function outputs data.
Description
Description
Video and Image Processing Suite User Guide
6–9