IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 85

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Register Bits
Register Bits
Table A–2. Control Word Specification Register
© March 2009 Altera Corporation
Bit
10
11
0
1
2
3
4
5
6
7
8
9
Count single-bit error
Correct single-bit error
Double-bit error enable
Reserved
Clear all status registers
Reserved
Reserved
Counter clear on read
Corrupt ECC enable
ECC corruption type
First or last error
Clear interrupt
Table A–2
Table A–3
Table A–3. Interrupt Status Register
Table A–4
Name
Others
Bit
0
1
2
3
4
shows the control word specification register.
shows the interrupt status register.
shows the interrupt mask register.
Single-bit error
Double-bit error
Maximum single-bit error
Maximum double-bit error
Double-bit error during read-
modify-write
Reserved
Decoder-corrector
Decoder-corrector
Decoder-corrector
N/A
Controller
N/A
N/A
Controller
Controller
Controller
Controller
Controller
Name
Direction
DDR and DDR2 SDRAM High-Performance Controller User Guide
When 1, single-bit error occurred.
When 1, double-bit error occurred.
When 1, single-bit error maximum threshold
exceeded.
exceeded.
When 1, double-bit error occurred during a read
modify write condition. (partial write).
Reserved.
When 1, double-bit error maximum threshold
When 1, count single-bit errors.
When 1, correct single-bit errors.
When 1, detect all double-bit errors and
increment double-bit error counter.
Reserved for future use.
When 1, clear counters single-bit error and
double-bit error status registers for first and last
error address.
Reserved for future use.
Reserved for future use.
When 1, enables counters to clear on read
feature.
When 1, enables deliberate ECC corruption
during encoding, to test the ECC.
When 0, creates single-bit errors in all ECC
codewords; when 1, creates double-bit errors in
all ECC codewords.
When 1, stores the first error address rather
than the last error address of single-bit error or
double-bit error.
When 1, clears the interrupt.
Description
Description
A–3