IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 57

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Figure 4–11. Half Rate Read, Avalon-MM Interface Mode—Non-Consecutive Read
Note to
(1) DDR Command and Mem Command show the command that the command signals are issuing.
© March 2009 Altera Corporation
Controller - PHY Interface (Non-AFI)
DDR Command (1)
Mem Command (1)
control_doing_rd[0]
control_rdata_valid
local_rdata_valid
local_burstbegin
PHY Memory Interface
local_read_req
local_address
control_rdata
mem_dqs[0]
local_ready
local_rdata
mem_cs_n
mem_addr
control_be
Figure
local_size
ddr_cs_n
mem_clk
mem_ba
mem_dq
phy_clk
Local Interface
ddr_ba
ddr_a
4–11:
4
802 804 806 808
[1]
0
0
[2]
RD
10
0
80A
[3]
0
10
RD
PCH
[6]
[4] [5]
ACT
8
A A
0
PCH
0
B
B
FF
RD
8
[10]
10
RD RD
1
ACT
[9]
8
DDR and DDR2 SDRAM High-Performance Controller User Guide
18
[12]
0
0
[11]
20
RD RD
RD
8
28
10
RD
[14]
0
RD
18
[13]
D D E E F F G G H H I I J J K K
20
RD RD
28
[8]
BBAA
BBAA
[7]
0
NOP
0
EEDD GGFF IIHH
EEDD
L
GGFF IIHH
L
[16]
0
4–29
[15]