IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 50

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–22
DDR and DDR2 SDRAM High-Performance Controller User Guide
The following sequence corresponds with the numbered items in
page
1. The user logic requests the first write, by asserting the local_write_req signal,
2. The controller issues the necessary memory command and address signals to the
3. The controller asserts the control_wdata_valid signal to indicate to the
4. The controller asserts the control_dqs_burst signals to control the timing of
5. The ALTMEMPHY megafunction issues the write command and sends the write
Half Rate Write, Native Interface Mode
Figure 4–8 on page 4–23
using the Local Interface Protocol setting set to Native interface. The figure shows
three back-to-back write requests, each of burst length 1 to sequential addresses. Each
request on the native interface maps directly to a single write burst of the length of 4
on the memory side because the controller is in half-rate mode. In half-rate, the ratio
between the width of the local interface write data bus and the memory data bus is
4:1.
and the size and address for this write. In this example, the request is a burst of
length 1 (4 on the memory side) to chip select 1. The local_ready signal is
asserted, which indicates that the controller has accepted this request, and the user
logic can request another read or write in the following clock cycle. If the
local_ready signal was not asserted, the user logic must keep the write request,
size, and address signals asserted until the local_ready signal is registered
high.
f
1
ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction that valid write data and write data masks are
present on the inputs to the ALTMEMPHY megafunction.
the DQS signal that the ALTMEMPHY megafunction issues to the memory.
f
data and write DQS to the memory.
4–21.
local_be is active high while mem_dm is active low.
Refer to
Refer to the “Handshake Mechanism Between Write Commands and
Write Data” section of the
User Guide (ALTMEMPHY)
Avalon Interface Specifications
shows write accesses with a controller in half-rate mode and
External Memory PHY Interface Megafunction
for more details of this interface.
for more details.
Chapter 4: Functional Description
© March 2009 Altera Corporation
Figure 4–7 on
Interfaces and Signals