IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 74

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–2
Understanding the Example Design and Testbench
Testbench Description
DDR and DDR2 SDRAM High-Performance Controller User Guide
f
4. Under Show in ‘Memory Presets’ List, set the following values:
5. Under Memory Presets, select Micron MT47H64M8CB-3.
6. Click Modify parameters and in the Preset Editor page, select 1 pair for the
7. In the Controller Settings tab on the Parameter Settings page, under
Refer to the
The MegaWizard Plug-In Manager helps you create an example design that shows
how to instantiate and connect both the DDR or DDR2 SDRAM high-performance
controller, and the ALTMEMPHY megafunction. This example allows you to quickly
create a working design.
The MegaCore function uses this example design in a testbench by connecting it to a
generic memory model and providing the required clock_source and
global_reset_n stimulus automatically.
The example design consists of the following blocks or components:
■
■
■
The respective DDR and DDR2 SDRAM high-performance controllers provide a
complete example of how to connect the ALTMEMPHY megafunction to a third party
controller. Refer to the “Integrating with Your Own Controller” section of the
Memory PHY Interface Megafunction User Guide (ALTMEMPHY)
information.
The generated example driver uses a simple LFSR structure to write data to the
attached memory device (or model) and, read it back to perform a comparison
between the read and write data. The example driver can be used as a placeholder for
a customer specific design. It can also be used to check if your memory interface is
working in hardware.
a. Select Micron for Memory Vendor.
b. Select Discrete Device for Memory format.
c. Set Maximum memory frequency to 333.333 MHz.
Outlook clock pairs from FPGA.
1
Controller/Phy Interface Protocol, select non-AFI.
ALTMEMPHY megafunction
memory controller
example driver
When specifying the PLL reference clock frequency and Memory clock
frequency, it is important to set values that result in small M and N values
within the PLL. For example, setting 133.33 MHz, 266.66 MHz, 333.33 MHz,
or 166.67 MHz may result in smaller M and N values compared to setting
133.0 MHz, 267.0 MHz, 333.0 MHz, or 167.0 MHz
ALTPLL Megafunction User Guide
for further information on PLL.
Understanding the Example Design and Testbench
Chapter 5: Example Design Walkthrough
© March 2009 Altera Corporation
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