IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 43

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Figure 4–5. Full Rate Write, Avalon-MM Interface
Note to
(1) DDR Command and Mem Command show the command that the command signals are issuing.
© March 2009 Altera Corporation
Controller - PHY Interface (Non-AFI)
control_wdata_valid
DDR Command
Mem Command
control_dqs_burst
local_burstbegin
local_write_req
local_read_req
Figure
control_wdata
PHY - Memory Interface
local_address
local_wdata
local_ready
mem_cs_n
mem_addr
control_be
local_size
mem_dqs
mem_dm
ddr_cs_n
mem_clk
mem_ba
mem_dq
Local Interface
local_be
phy_clk
ddr_ba
4–5:
ddr_a
(1)
(1)
00
AA
BB
[1]
2
NOP
CC
02
FF
[2]
DD
EE
04
FF
WR NOP
[3]
00
WR
AA
04
NOP
[4]
DDR and DDR2 SDRAM High-Performance Controller User Guide
0
NOP
BB
00
WR NOP
00
CC
FF
WR
08
[5]
00
A A
DD
WR
04
B B
[6]
EE
NOP
00
C C
NOP
FF
0
[7]
WR
08
D
D
00
NOP
E
E F
F
4–15