IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 30

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–2
Block Description
Figure 4–2. DDR and DDR2 SDRAM High-Performance Controller Architecture Block Diagram
DDR and DDR2 SDRAM High-Performance Controller User Guide
Avalon-MM or Native
Slave Interface
Figure 4–1
controller in non-AFI mode.
Figure 4–1. DDR and DDR2 SDRAM High-Performance Controller (Non-AFI) Block Diagram
Note to
(1) DDR2 SDRAM high-performance controller only.
Figure 4–2
controller architecture.
Figure
Command
Write Data
FIFO
FIFO
shows a block diagram of the DDR or DDR2 SDRAM high-performance
shows a block diagram of the DDR or DDR2 SDRAM high-performance
4–1:
local_powerdn_ack
local_self_rfsh_ack
local_powerdn_req
local_self_rfsh_req
local_refresh_ack
local_refresh_req
local_rdata_valid
local_burstbegin
local_wdata_req
local_write_req
local_init_done
local_read_req
Tracking Logic
Write Data
local_wdata
local_ready
local_rdata
local_addr
local_size
Timer
Logic
local_be
Main State
Machine
State Machine
DDR/DDR2 SDRAM High-
Initialization
Performance Controller
Management
ALTMEMPHY
Megafunction
(Encrypted)
Bank
Logic
Control
Logic
PHY Interface
Address and
Command
Decode
Logic
mem_a
mem_ba
mem_cas_n
mem_cke
mem_cs_n
mem_dq
mem_dqs
mem_dm
mem_odt ( 1 )
mem_ras_n
mem_we_n
Chapter 4: Functional Description
© March 2009 Altera Corporation
Block Description
ALTMEMPHY
Interface