IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 69

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Table 4–7. Local Interface Signals (Part 3 of 4)
© March 2009 Altera Corporation
local_write_req
local_init_done
local_rdata[]
local_rdata_error
local_rdata_valid
local_ready
local_refresh_ack
local_wdata_req
local_autopch_req
Signal Name
Direction
Output
Output
Output
Output
Output
Output
Output
Input
Input
Write request signal.
You cannot assert read request and write request signal at the same time.
When the memory initialization, training, and calibration are complete, the
ALTMEMPHY sequencer asserts the ctrl_usr_mode_rdy signal to the
memory controller, which then asserts this signal to indicate that the memory
interface is ready to be used.
Read and write requests are still accepted before local_init_done is
asserted, however they are not issued to the memory until it is safe to do so.
This signal does not indicate that the calibration is successful. To find out if the
calibration is successful, look for the calibration signal,
resynchronization_successful or postamble_successful
(for Stratix IV).
Read data bus. The width of local_rdata is twice that of the memory data
bus for a full rate controller; four times the memory data bus for a half rate
controller.
Asserted if the current read data has an error. This signal is only available if the
Enable error detection and correction logic is turned on.
Read data valid signal. The local_rdata_valid signal indicates that
valid data is present on the read data bus.
The local_ready signal indicates that the DDR or DDR2 SDRAM high-
performance controller is ready to accept request signals. If local_ready
is asserted in the clock cycle that a read or write request is asserted, that
request has been accepted. The local_ready signal is deasserted to
indicate that the DDR or DDR2 SDRAM high-performance controller cannot
accept any more requests. The controller is able to buffer four read or write
requests.
Refresh request acknowledge, which is asserted for one clock cycle every time
a refresh is issued. Even if the Enable user auto-refresh controls option is not
selected, local_refresh_ack still indicates to the local interface that the
controller has just issued a refresh command.
Write data request signal, which indicates to the local interface that it should
present valid write data on the next clock edge. This signal is only required
when the controller is operating in Native interface mode.
User control of precharge. If Enable auto precharge control is turned on,
local_autopch_req becomes available and you can request the
controller to issue an auto-precharge write or auto-precharge read command.
These commands cause the memory to issue a precharge command to the
current bank at the appropriate time without an explicit precharge command
from the controller. This is particularly useful if you know the current read or
write is the last one you intend to issue to the currently open row. The next
time you need to use that bank, the access could be quicker as the controller
does not need to precharge the bank before activating the row you wish to
access.
DDR and DDR2 SDRAM High-Performance Controller User Guide
Description
4–41