IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 84

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

A–2
Table A–1. ECC Registers (Part 2 of 2)
DDR and DDR2 SDRAM High-Performance Controller User Guide
Last single-bit error error
data
Last single-bit error
syndrome
Last double-bit error error
data
Interrupt status register
Interrupt mask register
Single-bit error location
status register
Double-bit error location
status register
Name
Address
0A
0B
0C
0D
07
08
09
(Bits)
Size
32
32
32
32
32
5
5
Attribute
R/W
R/W
WO
RO
RO
RO
RO
00000000
00000000
00000000
00000000
00000001
00000000
00000000
Default
This status register stores the last single-
bit error error data word. As the data
word is an Nth multiple of 64, the data
word is stored in a 2N-deep, 32-bit wide
FIFO buffer with the least significant 32-
bit sub word stored first. It can be cleared
individually by using the control word
clear.
This status register stores the last single-
bit error syndrome, which specifies the
location of the error bit on a 64-bit data
word. As the data word is an Nth multiple
of 64, the syndrome is stored in a N deep,
8-bit wide FIFO buffer where each
syndrome represents errors in every 64-
bit part of the data word. The register
gets updated with the correct syndrome
depending on which part of the data word
is shown on the last single-bit error error
data register. It can be cleared
individually by using the control word
clear.
This status register stores the last
double-bit error error data word. As the
data word is an Nth multiple of 64, the
data word is stored in a 2N deep, 32-bit
wide FIFO buffer with the least significant
32-bit sub word stored first. It can be
cleared individually by using the control
word clear.
This status register stores the interrupt
status in four fields (refer to
These status bits can be cleared by
writing a 1 in the respective locations.
This register stores the interrupt mask in
four fields (refer to
This status register stores the occurrence
of single-bit error for each 64-bit part of
the data word in every bit (refer to
Table
cleared by writing a 1 in the respective
locations.
This status register stores the occurrence
of double-bit error for each 64-bit part of
the data word in every bit (refer to
Table
cleared by writing a 1 in the respective
locations.
A–5). These status bits can be
A–6). These status bits can be
© March 2009 Altera Corporation
Description
Table
A–4).
Table
ECC Registers
A–3).