IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 36

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IPR-SDRAM/HPDDR2

Manufacturer Part Number
IPR-SDRAM/HPDDR2
Description
IP CORE Renewal Of IP-SDRAM/HDDR2
Manufacturer
Altera
Datasheet

Specifications of IPR-SDRAM/HPDDR2

Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Stratix FPGAs, Quartus II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
4–8
DDR and DDR2 SDRAM High-Performance Controller User Guide
Figure 4–3
Figure 4–3. ECC Block Diagram
The ECC comprises the following blocks:
The encoder—encodes the 64-bit message to a 72-bit codeword
The decoder-corrector—decodes and corrects the 72-bit codeword if possible
The ECC controller—controls multiple encoder and decoder-correctors, so that the
ECC can handle different bus widths. Also, it controls the following functions of
the encoder and decoder-corrector:
Interrupts:
Configuration registers:
Status registers:
Error signal—an error signal corresponding to the data word is provided with
the data and goes high if a double-bit error that cannot be corrected occurs in
the return data word.
Detected and corrected single-bit error
Detected double-bit error
Single-bit error counter threshold exceeded
Double-bit error counter threshold exceeded
Single-bit error detection counter threshold
Double-bit error detection counter threshold
Capture status for first encountered error or most recent error
Enable deliberate corruption of ECC for test purposes
Error address
Error type: single-bit error or double-bit error
Respective byte error ECC syndrome
shows the ECC block diagram.
Local Interface
To and From
From Local
To Local
Interface
Interface
N x 64 Bits
Message
N x 64 Bits
Message
Write
32 Bits
Read
Controller
Decoder-
Corrector
Encoder
ECC
ECC
N x 72 Bits
Codeword
N x 72 Bits
Codeword
Write
Read
Controller
Memory
N x 72 Bits
Chapter 4: Functional Description
© March 2009 Altera Corporation
DDR or DDR2
SDRAM
Block Description

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