IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 61

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
© March 2009 Altera Corporation
The following sequence corresponds with the numbered items in
page
1. The user logic requests the first read by asserting the read request signal. In this
2. The controller issues the first memory read command and address signals to the
3. The controller asserts the control_doing_rd signal to indicate to the
4. The ALTMEMPHY megafunction issues the first read commands to the memory
5. The memory returns the first read data to the ALTMEMPHY megafunction
6. The ALTMEMPHY megafunction returns the data to the controller by asserting
7. The controller returns the first read data to the user logic by asserting the
8. The user logic requests the first write by asserting the write request signal. In this
9. In native interface mode, the controller requests write data and byte enables from
10. The controller issues the first memory write command and address signals to the
11. The controller asserts the control_wdata_valid signal to indicate to the
12. The ALTMEMPHY megafunction issues the write command and sends the first
13. The user logic requests the second read by asserting the read request signal. In this
14. The controller issues the second memory read command and address signals to
15. The controller asserts the control_doing_rd signal to indicate to the
example, the request is a burst length of 1. The local_ready signal is asserted,
which indicates that the controller has accepted this request, and the user logic can
request another read or write in the following clock cycle.
ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction how many clock cycles of read data it should expect.
The ALTMEMPHY megafunction uses the control_doing_rd signal to enable
its capture registers for the expected duration of the memory burst.
f
and captures the read data from the memory.
(0xFF00).
control_rdata_valid.
local_rdata_valid signal when there is a valid read data on the
local_rdata bus.
example, the request is a burst length of 1.
the user logic by asserting local_wdata_req. The local_wdata (0xAABB) and
local_be signals must be presented within 1 clock cycle after the
local_wdata_req is asserted.
ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction that valid write data and write data masks are
present on the inputs to the ALTMEMPHY megafunction.
write data and write DQS to the memory.
example, the request is a burst length of 2.
the ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction how many clock cycles of read data it should expect.
4–32.
Refer to the “Handshake Mechanism Between Read Command and Read
Data” section of the
Guide (ALTMEMPHY)
External Memory PHY Interface Megafunction User
for more details of this interface.
DDR and DDR2 SDRAM High-Performance Controller User Guide
Figure 4–12 on
4–33