IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 13
IPR-SDRAM/HPDDR2
Manufacturer Part Number
IPR-SDRAM/HPDDR2
Description
IP CORE Renewal Of IP-SDRAM/HDDR2
Manufacturer
Altera
Datasheet
1.IP-SDRAMHPDDR.pdf
(88 pages)
Specifications of IPR-SDRAM/HPDDR2
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Stratix FPGAs, Quartus II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Design Flow
© March 2009 Altera Corporation
Figure 2–1
High-Performance Controller MegaCore function and the Quartus II software. The
sections in this chapter describe each stage.
Figure 2–1. Design Flow
shows the stages for creating a system with the DDR and DDR2 SDRAM
MegaWizard Plug-In
Manager Flow
Specify Parameters
Example Design
Simulate the
Perform Post-Compilation
Program Device and
Compile the Design
Select Design Flow
Implement Design
Add Constraints
Timing Analysis
DDR and DDR2 SDRAM High-Performance Controller User Guide
Specify Parameters
Simulate System
Complete SOPC
Builder System
2. Getting Started
SOPC Builder
Flow
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