IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 47

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
© March 2009 Altera Corporation
The following sequence corresponds with the numbered items
page
1. The user logic initiates the first write by asserting local_write_req signal, and
2. The user logic initiates a second write to a different memory row within the same
3. In native mode, the controller requests write data and byte enables by asserting
4. The controller continues to accept commands until the command queue is full.
5. As the local_ready is deasserted for one clock cyle, the user logic keeps the
6. The controller issues the first write memory command and column address
7. The controller asserts the control_wdata_valid signal to indicate to the
8. The controller asserts the control_dqs_burst signals to control the timing of
the size and address for this write. In this example, the request is a burst length of
2 to local address 0x000004. This local address is mapped to the following
memory address in full-rate mode.
mem_row_address = 0x0000
mem_col_address = 0x0004<<1 = 0x0008
mem_bank_address = 0x00
The local_ready signal is asserted, which indicates that the controller has
accepted this request, and the user logic can request another read or write in the
following clock cycle. If the local_ready signal is not asserted, the user logic
must keep the write request, size, and address signals asserted until the
local_ready signal is registered high.
bank. The request for the second write is a burst length is 2 to local address
0x000004. In this example, the user logic continues to request subsequent writes
to addresses 0x000804, 0x000806, 0x000808 and 0x00080A. The starting
address, 0x000802 is mapped to the following memory address in full-rate mode.
mem_row_address = 0x0004
mem_col_address = 0x0002<<1 = 0x0004
mem_bank_address = 0x00
local_wdata_req signal. The local_wdata and local_be signals must be
asserted within one clock cycle after the local_wdata_req signal. In this
example, the controller also continues to request write data for the subsequent
writes. The user logic must be able to supply the write data for the entire burst
when it requests a write.
First write local_wdata =
Second write local_wdata = <CC> <DD> to local_address = 0x000802
When the command queue is full, the controller deasserts the local_ready
signal indicating that it has not accepted the command.
write_req, local_address, local_size, and local_wdata signals for two
clock cycles until the local_ready signal is asserted again.
(0x0008) to the ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction that valid write data and write data masks are
present on the inputs to the ALTMEMPHY megafunction.
the DQS signal that the ALTMEMPHY megafunction issues to the memory.
4–18.
<AA> <BB> to local_address = 0x000004
DDR and DDR2 SDRAM High-Performance Controller User Guide
Figure 4–6 on
4–19