IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 49

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Figure 4–7. Half Rate Write, Avalon-MM Interface Mode
Note to
(1) DDR Command and Mem Command show the command that the command signals are issuing.
© March 2009 Altera Corporation
control_wdata_valid
control_dqs_burst[0]
DDR Command (1)
Mem Command (1)
Controller - PHY Interface (Non-AFI)
local_wdata_valid
PHY Memory Interface
local_burstbegin
local_write_req
control_wdata
local_address
Local Interface
mem_dqs[0]
Figure
local_wdata
local_ready
mem_cs_n
mem_addr
control_be
local_size
ddr_cs_n
mem_clk
mem_ba
mem_dq
local_be
phy_clk
ddr_ba
ddr_a
4–7:
AAAA
0000
0004
BBBB CCCC DDDD EEEE
[1]
0008
000C
0010
0000
0004
WR
AAAA
FFFF
0008
[2]
BBBB
000C
DDR and DDR2 SDRAM High-Performance Controller User Guide
CCCC DDDD EEEE
0010
0000
0000
WR
0004
[3]
WR
A A A A B B B B C C C C D D D D E E E E
NOP
0008
WR
[4]
000C
WR
0010
WR
[5]
4–21