IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 18

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–6
Table 2–3. Generated Files (Part 1 of 2)
DDR and DDR2 SDRAM High-Performance Controller User Guide
<variation name>.bsf
<variation name>.html
<variation name>.v or .vhd
<variation name>.qip
<variation name>.ppf
<variation name>_auk_ddr_hp_controller_wrapper.vo or .vho
<variation name>_example_driver.v or .vhd
<variation name>_example_top.v or .vhd
alt_mem_phy_defines.v
<variation_name>_phy.html
<variation_name>_phy.v/.vhd
<variation_name>_phy.vho
<variation_name>_phy_alt_mem_phy_delay.vhd
<variation_name>_phy_alt_mem_phy_dq_dqs.vhd or .v
8. After you review the generation report, click Exit to close the MegaWizard Plug-In
Manager.
Table 2–3
your project directory. The names and types of files specified in the MegaWizard
Plug-In Manager report vary based on whether you created your design with
VHDL or Verilog HDL.
Filename
describes the generated files and other files (AFI mode) that may be in
Quartus II symbol file for the MegaCore function
variation. You can use this file in the Quartus II block
diagram editor.
MegaCore function report file.
A MegaCore function variation file, which defines a
VHDL or Verilog HDL top-level description of the
custom MegaCore function. Instantiate the entity
defined by this file inside of your design. Include this
file when compiling your design in the Quartus II
software.
Contains Quartus II project information for your
MegaCore function variations.
This XML file describes the MegaCore pin attributes to
the Quartus II Pin Planner. MegaCore pin attributes
include pin direction, location, I/O standard
assignments, and drive strength. If you launch IP
Toolbench outside of the Pin Planner application, you
must explicitly load this file to use Pin Planner.
VHDL or Verilog HDL IP functional simulation model.
Example self-checking test generator that matches
your variation.
Example top-level design file that you should set as
your Quartus II project top level. Instantiates the
example driver and the controller.
Contains constants used in the interface. This file is
always in Verilog HDL regardless of the language you
chose in the MegaWizard Plug-In Manager.
Lists the top-level files created and ports used in the
megafunction.
Top-level file of your ALTMEMPHY variation, generated
based on the language you chose in the MegaWizard
Plug-In Manager.
Contains functional simulation model for VHDL only.
Includes a delay module for simulation. This file is only
generated if you choose VHDL as the language of your
MegaWizard Plug-In Manager output files.
Generated file that contains DQ/DQS I/O atoms
interconnects and instance. Arria II GX devices only.
Description
© March 2009 Altera Corporation
MegaWizard Plug-In Manager Flow
Chapter 2: Getting Started