IPR-SDRAM/HPDDR2 Altera, IPR-SDRAM/HPDDR2 Datasheet - Page 48

• Manufacturer Part Number: IPR-SDRAM/HPDDR2
• Description: IP CORE Renewal Of IP-SDRAM/HDDR2
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–20
DDR and DDR2 SDRAM High-Performance Controller User Guide
9. The ALTMEMPHY megafunction issues the write command and sends the write
10. The controller issues a PCH command to close current memory row (0x0000) and
11. The controller, then issues an ACT command to open next memory row (0x0004).
12. The controller also issues the next write memory command and column address
13. The ALTMEMPHY megafunction issues the PCH commands to the memory.
14. The ALTMEMPHY megafunction issues the ACT commands to the memory.
Half Rate Write, Avalon-MM Interface Mode
Figure 4–7 on page 4–21
using the Local Interface Protocol option set to Avalon Memory-Mapped interface.
The figure shows three back-to-back write requests of the same burst size. In half-rate
mode, the controller allows you to use burst size 1, which corresponds to a complete
memory burst of 4.
1
data and write DQS to the memory.
allow the second write to a different memory row (0x0004).
(0x0004) to the ALTMEMPHY megafunction for it to send to the memory device.
Refer to the "Handshake Mechanism Between Write Commands and Write
Data" section of the
(ALTMEMPHY)
shows write accesses with a controller in half-rate mode and
for more details of this interface.
External Memory PHY Interface Megafunction User Guide
Chapter 4: Functional Description
© March 2009 Altera Corporation
Interfaces and Signals