CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 97

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note: If the BMASK register is equal to the GMASK register,
the buffer 14 can be used the same way as the buffers 0 to
13.
The buffers 0 to 13 are scanned prior to buffer 14. Subse-
quently, the buffer 14 will not be checked for a matching ID
when one of the buffers 0 to 13 has already received a mes-
sage.
By setting the BUFFLOCK bit in the configuration register,
the receiving buffer is automatically locked after a reception
of one valid frame. The buffer will be unlocked again after the
CPU has read the data and has written RX_READY in the
buffer status field. With this lock function, the user has the ca-
pability to save several messages with the same identifier or
same identifier group into more than one buffer. For example,
20.5
All received frames will initially be buffered in a hidden re-
ceive buffer until the frame is valid. (The validation point for a
received message is the penultimate bit of EOF.) The re-
ceived identifier is then compared to every buffer ID together
with the respective mask and the status. As soon as the val-
idation point is reached, the whole contents of the hidden
buffer is copied into the matching message buffer as shown
in Figure60.
Note: The hidden receive buffer must not be accessed by
the CPU.
The following section gives an overview of the reception of
the different types of frames.
RECEIVE STRUCTURE
BUFFER14_ID
BUFFER13_ID
received ID
GMASK
BMASK
BUFFER0_ID
BUFFER1_ID
01010
Figure 59. Message Storage with BUFFLOCK Enabled
00000
01010
00000
01010
01010
01010
XXXXXXXX
XXXXXXXX
XXXXXXXX
10101010
XXXXXXXX
11111111
11111111
97
10101010
10101010
10101010
10101010
00000000
00000000
10101010
a buffer with the second highest priority will receive a mes-
sage if the buffer with the highest priority has already re-
ceived a message and is now locked (provided that both
buffers use the same acceptance filtering mask).
As shown in Figure59, several messages with the same ID
are received while BUFFLOCK is enabled. The filtering mask
of the buffers 0, 1, 13 and 14 is set to accept this message.
The first incoming frame will be received by buffer 0. As buff-
er 0 is now locked the next frame will be received by buffer 1,
and so on. If all matching receive buffers are full and locked,
a further incoming message will not be received by any buff-
er.
10101010
00000000
10101010
10101010
00000000
10101010
10101010
saved when buffer
saved when buffer
saved when buffer
saved when buffer
is empty
is empty
is empty
is empty
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