CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 112
![16-Bit Microcontroller IC](/photos/19/4/190456/3833527_sml.gif)
CR16MCS9VJE8
Manufacturer Part Number
CR16MCS9VJE8
Description
16-Bit Microcontroller IC
Manufacturer
National Semiconductor
Datasheet
1.CR16MCS9VJE8.pdf
(156 pages)
Specifications of CR16MCS9VJE8
Controller Family/series
CR16X
Core Size
16 Bit
Program Memory Size
64K X 8 Flash
Digital Ic Case Style
PQFP
No. Of Pins
80
Mounting Type
Surface Mount
Clock Frequency
25MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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20.9.9
The Can Timing Register (CTIM) defines the configuration of
the Bit Time Logic (BTL).
PSC[6:0]
SJW[1:0]
Note: The settings of SJW has to be configured to be small-
er or equal to TSEG1 and TSEG2
TSEG1[3:0] Time Segment 1. These bits configure the
15
PS
C6
SJW1
0
0
0
0
0
1
1
0
0
1
1
PSC[6:0]
PS
C5
CAN Timing Register (CTIM)
0
0
0
0
0
1
1
:
Table 31 CAN Prescaler Settings
SJW0
Prescaler Configuration. These bits set the
CAN prescaler. The settings are shown in
Table31
Synchronization Jump Width. These bits set
the Synchronization Jump Width which can be
programmed between 1 and 4 time quanta
(see Table32).
length of the Time Segment 1 (TSEG1). It is not
recommended to configure the time segment 1
to be smaller than 2tq. (see Table33).
0
1
0
1
PS
C4
0
0
0
0
0
1
1
:
Table 32 SJW Settings
9
PS
SJW[1:0] TSEG1[3:0] TSEG2[2:0]
C3
0
0
0
0
0
1
1
:
8
Synchronization Jump Width
r/w
7
PS
C2
0
0
0
0
0
1
1
1
:
6
PS
C1
0
0
1
1
0
0
1
:
(SJW)
1 tq
2 tq
3 tq
4 tq
PS
0/1
C0
0
1
0
1
0
1
:
3
2
prescaler
(PSC)
CAN
127
128
2
3
4
5
6
:
0
112
TSEG2[2:0] Time Segment 2. The TSEG2[2:0] bits set the
20.9.10 Global Mask Registers (GMSK — GMSKB and
The GMSKB and GMSKX registers allow you to globally
mask, or “don’t care” the incoming extended/standard identi-
fier bits, RTR/XRTR and IDE. Throughout this document, the
GMSKB and GMSKX 16-bit registers are referenced as a 32-
bit register GMSK.
TSEG
TSEG22
13
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
GMSKX)
Table 33 Time Segment 1 Settings
Table 34 Time Segment 2 Settings
TSEG
12
number of time quanta (tq) for phase segment
2 (see Table34).
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TSEG21
0
0
1
1
0
0
1
1
TSEG
11
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TSEG20
TSEG
0
1
0
1
0
1
0
1
10
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
not recommended
Length of Time
Length of
(TSEG1)
TSEG2
10 tq
12 tq
13 tq
14 tq
15 tq
16 tq
11 tq
2 tq
3 tq
4 tq
5 tq
6 tq
7 tq
8 tq
9 tq
1 tq
2 tq
3 tq
4 tq
5 tq
6 tq
7 tq
8 tq