CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 61

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

refers to timer subsystem 1 but equally applies to the other
three timer subsystems.
16.1.4
In case a timer subsystem is not used, the user can place it
in a low-power-mode. All clocks to a timer subsystem are
stopped and the counter and prescaler contents are frozen
once low-power-mode is entered. The user may continue to
write to the MODE, INTCTL, IOxCTL and CLKxPS registers.
Write operations to the INTPND register are allowed; but if a
timer subsystem is in low power mode, its associated inter-
rupt pending bits cannot be cleared. The user cannot write to
the COUNTx, PERCAPx and DTYCAPx registers of a timer
subsystem while it is in low-power-mode. All registers can be
read at any time.
16.1.5
The Versatile-Timer-Unit (VTU) has a total of 16 interrupt
sources, four for each of the four timer subsystems. All inter-
rupt sources have a pending flag and an enable bit associat-
16.1.6
The VTU supports breakpoint operation of the In-System-
Emulator (ISE). If FREEZE is asserted, all timer counter
clocks will be inhibited and the current value of the timer reg-
isters will be frozen; in capture mode, all further capture
events are disabled. Once FREEZE becomes inactive,
counting will resume from the previous value and the capture
input events are re-enabled.
IxAPD
IxBPD
IxCPD
IxDPD
Pending Flag
Figure 22. VTU Dual 16-bit Capture Mode
Low Power Mode
Interrupts
ISE Mode operation
cap
rst
15
2
C1EDG
Restart
0
TIO1
Low Byte Duty Cycle match
Low Byte Period match
High Byte Duty Cycle match
High Byte Period match
7
C1PRSC
Prescaler
T1RUN
Counter
==
PERCAP1[15:0]
DTYCAP1[15:0]
COUNT1[15:0]
0
Dual 8-bit PWM Mode
capture
capture
TMOD1=11
Table 17 VTU Interrupt Sources
cap
r s t
2
C2EDG
0
0
TIO2
[15:0]
61
Duty Cycle match
Period match
N/A
N/A
ed with them. All interrupt pending flags are denoted IxAPD
through IxDPD where “x” relates to the specific timer sub-
system. There is one system level interrupt request for each
of the four timer subsystems.
Figure23 illustrates the interrupt structure of the versatile
timer module.
Each of the timer pending flags - IxAPD through IxDPD - is
set by a specific hardware event depending on the mode of
operation, i.e., PWM or Capture mode. Table17 outlines the
specific hardware events relative to the operation mode
which cause an interrupt pending flag to be set.
16.2
The Versatile-Timer-Unit contains a total of 19 user accessi-
ble registers. All registers are word-wide and are initialized to
a known value upon reset. All software accesses to the VTU
registers must be word accesses.
I1APD
I1BPD
I1CPD
I1DPD
I4APD
I4BPD
I4CPD
I4DPD
16-bit PWM Mode
Figure 23. VTU Interrupt Request Structure
VTU REGISTERS
I1AEN
I1BEN
I1CEN
I1DEN
I4AEN
I4BEN
I4CEN
I4DEN
Capture to DTYCAPx
Capture to PERCAPx
Counter Overflow
N/A
Capture Mode
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System
Interrupt
Request 1
System
Interrupt
Request 4