CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 76

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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UnPSEL
UnPEN
18.3.6
The USART Mode Select Register is a byte-wide, read/write
register that selects the clock source, synchronization mode,
attention mode, and line break generation. This register is
cleared upon reset. When the software writes to this register,
the reserved bits must be cleared to 0 for proper operation.
The register format is shown below.
UnMOD
UnATN
UnBRK
UnCKS
18.3.7
The USART Status Register is a byte-wide, read-only regis-
ter that contains the receive and transmit status bits. This
register is cleared upon reset. Any attempt by the software to
write to this register is ignored. The register format is shown
below.
UnPE
Reserved UnXMIP
7
Reserved
7
6
5
USART Mode Select Register (UnMDSL)
USART Status Register (UnSTAT)
6
4
Parity Select. This 2-bit field selects parity type
as follows:
00 = odd parity
01 = even parity
10 = mark (0)
11 = space (1)
When the USART is configured to transmit nine
data bits per frame, the parity bit is omitted and
the UnPSEL field is ignored.
Parity Enable. This bit enables (1) or disables
(0) parity bit generation and parity checking.
When the USART is configured to transmit nine
data bits per frame, there is no parity bit and the
UnPEN bit is ignored.
Mode of Operation. Set to 0 for asynchronous
operation or 1 for synchronous operation.
Attention Mode. When set to 1, this bit selects
the attention mode of operation for the USART.
When cleared to 0, the attention mode is dis-
abled. The hardware clears this bit after an ad-
dress frame is received. An address frame is a
9-bit character with a 1 in the ninth bit position.
Force Transmission Break. Setting this bit to 1
causes the TDXn pin to go low. TDXn remains
low until the UnBRK bit is cleared to 0 by the
software.
Synchronous Clock Source. This bit controls
the clock source when the USART operates in
the synchronous mode (UnMOD=1). If the
UnCKS bit is set to 1, the USART operates
from an external clock provided on the CKXn
pin. If the UnCKS bit is cleared to 0, the USART
operates from the baud rate clock produced by
the USART on the CKXn pin. This bit is ignored
when the USART operates in the asynchro-
nous mode.
Parity Error. This bit is set to 1 when a parity er-
ror is detected within a received character. This
UnCKS
UnRB9
3
5
UnBKD UnERR UnDOE UnFE UnPE
4
UnBRK
2
3
UnATN
1
2
1
UnMOD
0
0
76
UnFE
UnDOE
UnERR
UnBKD
UnRB9
UnXMIP
18.3.8
The USART Interrupt Control Register is a byte-wide register
that contains the receive and transmit interrupt status flags
(read-only bits) and the interrupt enable bits (read/write bits).
The register is set to 01 hex upon reset. The register format
is shown below.
UnTBE
UnRBF
UnEEI
7
USART Interrupt Control Register (UnICTRL)
UnERI
6
bit is automatically cleared to 0 by the hard-
ware when the UnSTAT register is read.
Framing Error. This bit is set to 1 when the US-
ART fails to receive a valid stop bit at the end
of a frame. This bit is automatically cleared to 0
by the hardware when the UnSTAT register is
read.
Data Overrun Error. This bit is set to 1 when a
new character is received and transferred to
the UnBUF register before the software has
read the previous character from UnBUF. This
bit is automatically cleared to 0 by the hard-
ware when the UnSTAT register is read.
Error Status Flag. This bit is set when a parity,
framing, or overrun error occurs (any time that
the UnPE, UnFE, or UnDOE bit is set). It is au-
tomatically cleared to 0 by the hardware when
the UnPE, UnFE, and UnDOE bits are all 0.
Break Detect. This bit is set to 1 when a line
break condition occurs. This condition is de-
tected if RDXn remains low for at least ten bit
times after a missing stop bit has been detect-
ed at the end of a frame.
The hardware automatically clears the UnBKD
bit upon read of the UnSTAT register, but only
if the break condition on RXDn no longer ex-
ists. If reading the UnSTAT register does not
clear the UnBKD bit because the break is still
actively driven on the line, the hardware clears
the bit as soon as the break condition no longer
exists (when RXDn returns to a high level).
Received 9th Data Bit. With the USART config-
ured to operate in the 9-bit data format, this is
equal to the ninth data bit of the last frame re-
ceived.
Transmit In Progress. The hardware sets this
bit to 1 when the USART is transmitting data
and clears it to 0 at the end of the last frame bit.
Transmit Buffer Empty. This read-only bit is set
to 1 by the hardware when the USART trans-
fers data from the UnTBUF register to the
transmit shift register for transmission. It is au-
tomatically cleared to 0 by the hardware on the
next write to the UnTBUF register.
Receive Buffer Full. This read-only bit is set by
the hardware when the USART has received a
complete data frame and has transferred the
data from the receive shift register to the UnR-
BUF register. It is automatically cleared to 0 by
the hardware when the UnRBUF register is
read.
UnETI
5
Reserved
4
3
2
UnRBF
1
UnTBE
0