CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 75

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The interrupts can be individually enabled or disabled using
the Enable Transmit Interrupt (UnETI), Enable Receive Inter-
rupt (UnERI) and Enable Receive Error Interrupt (UnEER)
bits in the UnICTRL register.
A transmit interrupt is generated when both the UnTBE and
UnETI bits are set. To remove this interrupt, software must ei-
ther disable the interrupt by clearing the UnETI bit or write to
the UnTBUF register (thus clearing the UnTBE bit).
A receive interrupt is generated on two conditions:
18.2.8
A line break is generated when the BRK bit is set in the Un-
MDSL register. The TDXn line remains low until the program
resets the BRK bit.
A line break is detected if RDXn remains low for 10 bit times
or longer after a missing stop bit is detected.
18.2.9
Parity is only generated or checked with the 7-bit and 8-bit
data formats. It is not generated or checked in the diagnostic
loopback mode, the attention mode, or in the normal mode
with the 9-bit data format. Parity generation and checking are
enabled and disabled via the PEN bit in the UnFRS register.
The UnPSEL bits in the UnFRS register are used to select
odd, even, mark, or space parity.
18.3
The software interacts with the USART by accessing the US-
ART registers. There are eight such registers:
18.3.1
The USART Receive Data Buffer is a byte-wide, read/write
register used to receive each data byte.
18.3.2
The USART Transmit Data Buffer is a byte-wide, read/write
register used to transmit each data byte.
18.3.3
The USART Baud Rate Prescaler Register is a byte-wide,
read/write register that contains the 5-bit clock prescaler and
1. Both the UnRBF and UnERI bits are set. To remove this
2. Both the UnERR and the UnEEI bits are set. To remove
— USART Receive Data Buffer (UnRBUF)
— USART Transmit Data Buffer (UnTBUF)
— USART Baud Rate Prescaler Register (UnPSR)
— USART Baud Rate Divisor Register (UnBAUD)
— USART Frame Select Register (UnFRS)
— USART Mode Select Register (UnMDSL)
— USART Status Register (UnSTAT)
— USART Interrupt Control Register (UnICTRL)
interrupt, software must either disable the interrupt by
clearing the UnERI bit or read from the UnRBUF register
(thus clearing the UnRBF bit).
this interrupt the software must either disable it by clear-
ing the UnEEI bit or read the UnSTAT register (thus
clearing the UnERR bit).
Break Generation and Detection
Parity Generation and Detection
USART Receive Data Buffer (UnRBUF)
USART Transmit Data Buffer (UnTBUF)
USART Baud Rate Prescaler (UnPSR)
USART REGISTERS
75
the upper three bits of the baud rate divisor. This register is
cleared upon reset. The register format is shown below.
UnPSC
UnDIV[10:8] Baud Rate Divisor (bits 10-8). This field con-
18.3.4
The USART Baud Rate Divisor Register is a byte-wide, read/
write register that contains the lower eight bits of the baud
rate divisor. This register contents are unknown upon power-
up and are left unchanged by a reset operation. The register
format is shown below.
UnDIV[7:0]
18.3.5
The USART Frame Select Register is a byte-wide, read/write
register that controls the frame format, including the number
of data bits, number of stop bits, and parity type. This register
is cleared upon reset. The register format is shown below.
UnCHAR
UnSTP
UnXB9
UnDIV7 UnDIV6 UnDIV5 UnDIV4 UnDIV3 UnDIV2 UnDIV1 UnDIV0
Reserved UnPEN UnPSEL UnXB9 UnSTP UnCHAR
7
7
6 5 4 3
7
UnPSC
USART Baud Rate Divisor (UnBAUD)
USART Frame Select Register (UnFRS)
6
Prescaler. This 5-bit field specifies the prescal-
er value used for dividing the system clock in
the first stage of the two-stage divider chain.
For the prescaler factors corresponding to
each 5-bit value, see Table19.
tains the three highest-order bits (bits 10, 9,
and 8) of the USART baud rate divisor used in
the second stage of the two-stage divider
chain. The remaining bits of the baud rate divi-
sor are contained in the UnBAUD register.
Baud Rate Divisor (bits 7-0). This field contains
the eight lowest-order bits of the USART baud
rate divisor used in the second stage of the
two-stage divider chain. The three highest-or-
der bits are contained in the UnPSR register.
The divisor value used is the 11-bit UnDIV val-
ue plus 1.
Character Frame Format. This 2-bit field se-
lects the number of data bits per frame, not in-
cluding the parity bit, as follows:
00 = eight data bits per frame
01 = seven data bits per frame
10 = nine data bits per frame
11 = loopback mode; nine data bits per frame
Number of Stop Bits. This bit sets the number
of stop bits transmitted in each frame. If this bit
is 0, one stop bit is transmitted. If this bit is 1,
two stop bits are transmitted.
Transmit 9th Data Bit. This bit is the value of
the ninth data bit, either 0 or 1, transmitted
when the USART is configured to transmit nine
data bits per frame. It has no effect when the
USART is configured to transmit seven or eight
data bits per frame.
6
5
UnDIV10
5
2
4
4
3
3
UnDIV9
1
2
www.national.com
2
1
UnDIV8
1
0
0
0