CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 51

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15.2
Each timer/counter unit can be configured to operate in any
of the following modes:
Upon reset, the timers are disabled. To configure and start
the timers, the software must write a set of values to the reg-
isters that control the timers. The registers are described in
Section15.5.
On the first underflow, the timer is loaded from TnCRA, then
from TnCRB on the next underflow, then from TnCRA again
on the next underflow, and so on. Every time the counter is
stopped and restarted, it always obtains its first reload value
from TnCRA. This is true whether the timer is restarted upon
reset, after entering Mode 1 from another mode, or after
stopping and restarting the clock with the Timer/Counter I
clock selector.
The timer can be configured to toggle the TnA output bit upon
each underflow. This generates a clock signal on TnA with
the width and duty cycle determined by the values stored in
the TnCRA and TnCRB registers. This is a “processor-inde-
pendent” PWM clock because once the timer is set up, no
more action is required from the CPU to generate a continu-
ous PWM signal.
The timer can be configured to generate separate interrupts
upon reload from TnCRA and TnCRB. The interrupts can be
enabled or disabled under software control. The CPU can
— Processor-Independent
— Dual Input Capture mode
— Dual Independent Timer mode
— Single Input Capture and Single Timer mode
(PWM) mode
TIMER OPERATING MODES
Timer I
Timer II
Selector
Clock
Clock
Clock
Figure 14. Mode 1: Processor-Independent PWM Block Diagram
Pulse
Width
Reload A = Time 1
Reload B = Time 2
Timer/Counter I
Timer/Counter II
TnCNT1
Modulation
TnCRA
TnCNT2
TnCRB
Underflow
Underflow
51
15.2.1
Mode 1 is the Processor-Independent Pulse Width Modula-
tion (PWM) mode, which generates pulses of a specified
width and duty cycle, and which also provides a separate
general-purpose timer/counter.
Figure14 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 1. Timer/Counter I (TnCNT1)
functions as the time base for the PWM timer. It counts down
at the clock rate selected for the counter. When an underflow
occurs, the timer register is reloaded alternately from the
TnCRA and TnCRB register, and counting proceeds down-
ward from the loaded value.
determine the cause of each interrupt by looking at the
TnAPND and TnBPND flags, which are set by the hardware
upon each occurrence of a timer reload.
In Mode 1, Timer/Counter II (TnCNT2) can be used either as
a simple system timer, an external event counter, or a pulse
accumulate counter. The clock counts down using the clock
selected with the Timer/Counter II clock selector. It generates
an interrupt upon each underflow if the interrupt is enabled
with the TnDIEN bit.
15.2.2
Mode 2 is the Dual Input Capture mode, which measures the
elapsed time between occurrences of external events, and
which also provides a separate general-purpose timer/
counter.
Figure15 is a block diagram of the Multi-Function Timer con-
figured to operate in Mode 2. The time base of the capture
timer depends on Timer/Counter I, which counts down using
the clock selected with the Timer/Counter I clock selector.
Mode 1: Processor-Independent PWM
Mode 2: Dual Input Capture
TnAPND
TnDPND
TnBPND
TnDIEN
TnAIEN
TnBIEN
TnAEN
Interrupt B
Interrupt D
Interrupt A
Timer
Timer
Timer
www.national.com
TnA
TnB