CR16MCS9VJE8 National Semiconductor, CR16MCS9VJE8 Datasheet - Page 62

• Manufacturer Part Number: CR16MCS9VJE8
• Description: 16-Bit Microcontroller IC
• Manufacturer: National Semiconductor

Specifications of CR16MCS9VJE8

• Controller Family/series: CR16X
• Core Size: 16 Bit
• Program Memory Size: 64K X 8 Flash
• Digital Ic Case Style: PQFP
• No. Of Pins: 80
• Mounting Type: Surface Mount
• Clock Frequency: 25MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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16.2.1
The Mode Control (MODE) registries a word-wide read/write
register which controls the mode selection of all four timer
subsystems. The register is cleared (0000
TxRUN
TMODx
16.2.2
The I/O Control Register 1 (IO1CTL) is a word-wide read/
write register. The register controls the functionality of the
I/O pins TIO1 through TIO4 depending on the selected mode
of operation. The register is cleared (0000
CxEDG
P4POL
TMOD4
TMOD2
15
7
1 5
14
6
14
C4EDG P3POL C3EDG P2POL
Mode Control Register (MODE)
I/O Control Register 1 (IO1CTL)
T8RUN
T4RUN
12
Timer start/stop. If set (1), the associated
counter and clock prescaler is started depend-
ing on the mode of operation. Once set, the
clock to the clock prescaler and the counter are
enabled and the counter will increment each
time the clock prescaler counter value matches
the value defined in the associated clock pres-
caler field (CxPRSC).
Timer System Operating Mode. This 2-bit wide
field enables or disables the Timer Subsystem
and defines it’s operating mode.
00:
01:
10:
11:
Capture Edge Control. Defines the polarity of a
capture event and the reset of the counter. The
13
5
11
the counter subsystem are stopped. The
counter is stopped regardless of the val-
ue of the TxRUN bits. Read operations
to the Timer Subsystem will return the
last value; the user shall not perform any
write operations to the Timer Subsystem
while it is disabled since those will be ig-
nored.
Dual 8-bit PWM mode enabled. Each 8-
bit counter may individually be started or
stopped via its associated TxRUN bit.
The TIOx pins will function as PWM out-
puts.
16-bit PWM mode enabled. The two 8-
bit counters are concatenated to form a
single 16-bit counter. The counter may
be started or stopped with the lower of
the two TxRUN bits, i.e. T1RUN,
T3RUN, T5RUN and T7RUN. The TIOx
pins will function as PWM outputs.
Capture Mode enabled. Both 8-bit
counters are concatenated and operate
as a single 16-bit counter. The counter
may be started or stopped with the lower
of the two TxRUN bits, i.e., T1RUN,
T3RUN, T5RUN and T7RUN. The TIOx
pins will function as capture inputs.
Low-Power-Mode enabled. All clocks to
T7RUN
T3RUN
10
12
4
8
TMOD3
TMOD1
11
3
7
10
2
C2EDG P1POL C1EDG
6
1 6
T6RUN
T2RUN
1 6
4
) upon reset.
) upon reset.
9
1
3
T5RUN
T1RUN
2
8
0
0
62
PxPOL
Once a counter is stopped, the output will assume the value
of PxPOL, i.e., its initial value. The PxPOL bit has no effect
while operating in capture mode.
16.2.3
The I/O Control Register 2 (IO2CTL) is a word-wide read/
write register. The register controls the functionality of the
I/O pins TIO5 through TIO8 depending on the selected mode
of operation. The register is cleared (0000) upon reset.
The functionality of the bit fields of the IO2CTL register is
identical to the ones described in the IO1CTL register sec-
tion.
16.2.4
The Interrupt Control (INTCTL) register is a word-wide read/
write register. It contains the interrupt enable bits for all 16 in-
terrupt sources of the Versatile-Timer-Unit. Each interrupt en-
able bit corresponds to an interrupt pending flag located in
the Interrupt Pending Register (INTPND). All INTCTL regis-
ter bits are solely under software control. The register is
cleared (0000
IxAEN
P8POL C8EDG P7POL C7EDG P6POL C6EDG P5POL C5EDG
I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN
I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN
15
15
7
14
I/O Control Register 2 (IO2CTL)
Interrupt Control Register (INTCTL)
14
6
12
value of this three bit field has no effect while
operating in PWM mode.
PWM Polarity. While operating in PWM mode
the bit defines the output polarity of the corre-
sponding PWM output (TIOx).
0 =
1 =
Timer x interrupt A enable. Enable/Disable an
interrupt request based on the corresponding
IxAPD flag being set. The associated IxAPD
1 6
CxEDG
) upon reset..
11
13
000
001
010
011
100
101
110
111
5
The PWM output is set (1) upon the 00
to 01
be reset (0) once the counter value
matches the duty cycle value.
The PWM output is reset (0) upon the
00
will be set (1) once the counter value
matches the duty cycle value.
1 6
10
12
to 01
1 6
4
falling edge
falling edge
rising edge
rising edge
both edges
both edges
both edges
both edges
transition of the counter and will
Capture
8
16
11
transition of the counter and
7
3
6
10
2
Counter Reset
4
falling edge
rising edge
both edges
3
Yes
Yes
No
No
No
9
1
2
8
0
0
16