MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 92
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Electrical Characteristics
4.7.8.7
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of
the interface is described in
92
2
3
Display interface clock down time
Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Interface to a TV Encoder (TVDAC)
•
•
•
•
•
•
The frequency of the clock DISP_CLK is 27 MHz (within 10%)
The HSYNC, VSYNC signals are active low.
The DRDY signal is shown as active high.
The transition to the next row is marked by the negative edge of the
HSYNC signal. It remains low for a single clock cycle.
The transition to the next field/frame is marked by the negative edge of
the VSYNC signal. It remains low for at least one clock cycles.
—
of VSYNC and HSYNC coincide.
—
coincide.
The active intervals—during which data is transferred—are marked by
the HSYNC signal being high.
At a transition to an odd field (of the next frame), the negative edges
At a transition is to an even field (of the same frame), they do not
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Figure
Tdicd
Tdicu
49.
=
=
1
-- - T diclk
2
⎛
⎝
1
-- - T diclk
2
⎛
⎝
×
ceil
×
NOTE
ceil
2
---------------------------------------------------------- -
×
2
----------------------------------------------- -
DI_CLK_PERIOD
DI_CLK_PERIOD
DISP_CLK_DOWN
×
DISP_CLK_UP
⎞
⎠
⎞
⎠
Freescale Semiconductor
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