MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 120
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Electrical Characteristics
1
2
4.7.12.3 UDMA Output Timing
Figure 73
host terminates transfer,
Table 73
120
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
Make ton and toff big enough to avoid bus contention.
Parameter
tdzfs
ATA
tzah
tcyc
tcvh
tmli
trp
—
—
lists the timing parameters for UDMA out burst.
shows timing when the UDMA out transfer starts,
Parameter
Figure
Figure
Figure 72
from
tmli1
tdzfs
tzah
tx1
tcvh
toff
ton
tc1
trp
1
2
70,
71,
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Figure 75
Table 72. UDMA in Burst Timing Parameters (continued)
Figure 73. UDMA Out Transfer Starts Timing Diagram
(tcyc – tskew) > T
trp (min) = time_rp
(time_rp
tmli1 (min) = (time_mlix + 0.4)
tzah (min) = (time_zah + 0.4)
tdzfs = (time_dzfs
tcvh = (time_cvh
ton = time_on
toff = time_off
shows timing when the UDMA out device terminates transfer, and
×
T) – (tco + tsu + 3T + 2
×
×
T – tskew1
T – tskew1
×
×
T) – (tskew1 + tskew2)
×
T) – (tskew1 + tskew2)
T – (tskew1 + tskew2 + tskew6)
Description
×
×
T
T
×
tbuf + 2
Figure 74
×
tcable2) > trfs (drive)
shows timing when the UDMA out
Freescale Semiconductor
Controlling Variable
T big enough
time_dzfs
time_mlix
time_zah
time_cvh
time_rp
time_rp
—
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