MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 5
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 5 of 204
- Download datasheet (2Mb)
The system supports efficient and smart power control and clocking:
Security functions are enabled and accelerated by the following hardware:
Freescale Semiconductor
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— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up
Expansion cards:
— Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port
USB
— High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY
— Three USB 2.0 (480 Mbps) hosts:
— One-wire (OWIRE) port
— Three I2S/SSI/AC97ports, supporting up to 1.4 Mbps, each connected to audio multiplexer
— Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support
— Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port
— Three I
— Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps
— Two controller area network (FlexCAN) interfaces, 1 Mbps each
— Sony Phillips Digital Interface (SPDIF), Rx and Tx
— Enhanced serial audio interface (ESAI), up to 1.4 Mbps each channel
— Key pad port (KPP)
— Two pulse-width modulators (PWM)
— GPIO with interrupt capabilities
— Secure JTAG controller (SJC)
Supporting DVFS (dynamic voltage and frequency scaling) technique for low power modes
Power gating SRPG (State Retention Power Gating) for ARM core and Neon
Support for various levels of system power modes
Flexible clock gating control scheme
On-chip temperature monitor
On-chip oscillator amplifier supporting 32.768 kHz external crystal
On-chip LDO voltage regulators for PLLs
ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so
on)
Miscellaneous interfaces:
to 120-MHz peak clock frequency.
supporting 832 Mbps (8-bit, eMMC 4.4).
– High-speed host with integrated on-chip high-speed PHY
– Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB
(AUDMUX) providing four external ports.
4-wire.
2
C ports, supporting 400 kbps
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Introduction
5
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