MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 159
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 159 of 204
- Download datasheet (2Mb)
Freescale Semiconductor
DISP0_DAT9
DRAM_A0
DRAM_A1
DRAM_A10
DRAM_A11
DRAM_A12
DRAM_A13
DRAM_A14
DRAM_A15
DRAM_A2
DRAM_A3
DRAM_A4
DRAM_A5
DRAM_A6
DRAM_A7
DRAM_A8
DRAM_A9
DRAM_CALIB
RATION
DRAM_CAS
DRAM_CS0
DRAM_CS1
Package Pin
Name
E2
M19
L21
K19
L22
L20
L23
N18
M18
M20
N20
K20
N21
M22
N22
N23
M21
M23
L18
K18
P19
Table 110. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Assign
ment
Pin
i.MX53xD Applications Processors for Consumer Products, Rev. 1
NVCC_LCD
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
NVCC_EMI_DRAM
Power Rail
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
DDR3
special
DDR3
DDR3
DDR3
GPIO
DDR3
DDR3
DDR3
DDR3
DDR3
I/O Buffer
Type
Mode
ALT1
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
—
ALT0
ALT0
ALT0
Alt.
GPIO-4 gpio4_GPIO[30]
EXTMC emi_DRAM_A[0]
EXTMC emi_DRAM_A[1]
EXTMC emi_DRAM_A[10
EXTMC emi_DRAM_A[11
EXTMC emi_DRAM_A[12
EXTMC emi_DRAM_A[13
EXTMC emi_DRAM_A[14
EXTMC emi_DRAM_A[15
EXTMC emi_DRAM_A[2]
EXTMC emi_DRAM_A[3]
EXTMC emi_DRAM_A[4]
EXTMC emi_DRAM_A[5]
EXTMC emi_DRAM_A[6]
EXTMC emi_DRAM_A[7]
EXTMC emi_DRAM_A[8]
EXTMC emi_DRAM_A[9]
—
EXTMC emi_DRAM_CAS
EXTMC emi_DRAM_CS[
EXTMC emi_DRAM_CS[
Package Information and Contact Assignments
Out of Reset Condition
]
]
]
]
]
]
(used in DRAM
driver calibration.
See Special
Signal
Considerations
{add xref} above)
0]
1]
Block I/O
Directio
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
n
1
100 KΩ PU
Config./
Value
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
—
159
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