MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 152

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Boot Mode Configuration
5.3
By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In order to
achieve the standard operating mode (see VDD_DIG_PLL on
should be configured by software by boot code after power-up to 1.3 V output. This is done by
programming the PLL1P2_VREG bits.
152
NAND Flash
Interface
SD/MMC
SD/MMC
SD/MMC
SD/MMC
UART
UART
UART
UART
UART
SATA
PATA
USB
EIM
I2C
I2C
I2C
Power setup during Boot
eSDHCv2-1 PATA_DATA[11:8], SD1_DATA[3:0], SD1_CMD,
eSDHCv2-2 PATA_DATA[15:12], SD2_CLK, SD2_CMD,
eSDHCv3-3 PATA_RESET_B, PATA_IORDY, PATA_DA_0,
eSDHCv2-4 PATA_DA1, PATA_DA_2, PATA_DATA[7:4],
IP Instance
SATA_PHY
UARTv2-1
UARTv2-2
UARTv2-3
UARTv2-4
UARTv2-5
USB-OTG
EXTMC
I2C-1
I2C-2
I2C-3
PATA
PHY
EIM
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Table 108. Interfaces Allocation During Boot (continued)
EIM
NAND
SD1_CLK
SD2_DATA[3:0]
PATA_DATA[3:0], PATA_DATA[11:8]
PATA_DATA[15:12]
EIM_D21, EIM_D28
EIM_D16, EIM_EB2
EIM_D[18:17]
PATA_DIOW, PATA_DMACK, PATA_DMARQ,
PATA_BUFFER_EN, PATA_INTRQ, PATA_DIOR,
PATA_RESET_B, PATA_IORDY, PATA_DA_[2:0],
PATA_CS_[1:0], PATA_DATA[15:0]
SATA_TXM, SATA_TXP, SATA_RXP, SATA_RXM,
SATA_REXT, SATA_REFCLKM, SATA_REFCLKP
CSI0_DAT[11:10]
PATA_DMARQ, PATA_BUFFER_EN
EIM_D24, EIM_D25
CSI0_DAT[13:12]
CSI0_DAT[15:14]
USB_H1_GPANAIO
USB_H1_RREFEXT
USB_H1_DP
USB_H1_DN
USB_H1_VBUS
Allocated Pads During Boot
Table
6), LDO output to VDD_DIG_PLL
1, 4 or 8 bit
1, 4 or 8 bit
1, 4 or 8 bit
1, 4 or 8 bit
RXD/TXD only
RXD/TXD only
RXD/TXD only
RXD/TXD only
RXD/TXD only
• Lower 16 bit data bus A/D
• Only CS0 is supported.
• 8/16 bit
• NAND data can be muxed either over
• Only CS0 is supported
multiplexed or upper 16 bit data bus
non multiplexed
EIM data or PATA data
Comment
Freescale Semiconductor
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