MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 66

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
4.7.2.2
Figure 31
characteristics.
4.7.2.3
Figure 30
characteristics.
66
SSx
SCLK
MISO
MOSI
CS1
CS2
CS3
CS4
ID
CS1
CS2
CS4
CS5
CS6
CS7
CS8
CS9
ID
depicts the timing of CSPI in slave mode.
depicts the timing of ECSPI in master mode.
CS7
SCLK Cycle Time–Read
SCLK Cycle Time–Write
SCLK High or Low Time–Read
SCLK High or Low Time–Write
SCLK Rise or Fall
SSx pulse width
SCLK Cycle Time
SCLK High or Low Time
SSx pulse width
SSx Lead Time (SS setup time)
SSx Lag Time (SS hold time)
MOSI Setup Time
MOSI Hold Time
MISO Propagation Delay (C
CSPI Slave Mode Timing
ECSPI Master Mode Timing
CS9
i.MX53xD Applications Processors for Consumer Products, Rev. 1
CS1
CS8
1
Figure 31. CSPI/ECSPI Slave Mode Timing Diagram
Table 43. ECSPI Master Mode Timing Parameters
Parameter
Table 42. CSPI Slave Mode Timing Parameters
Parameter
LOAD
= 20 pF)
Table 42
CS2
Table 43
Symbol
t
t
t
t
PDmiso
t
CS2
RISE/FALL
t
t
Smosi
Hmosi
Symbol
CSLH
t
HCS
SCS
t
SW
t
clk
CSLH
t
lists the CSPI slave mode timing
t
SW
clk
lists the ECSPI master mode timing
Half SCLK period
CS6
Min
100
0
Min
30
15
14
—
7
CS4
Freescale Semiconductor
Max
—
—
—
—
—
—
—
Max
—
—
—
—
CS5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns