MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 118
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Electrical Characteristics
4.7.12.2 Ultra DMA (UDMA) Input Timing
Figure 70
host terminates transfer,
Table 72
118
1
2
Parameter
tk1 in the MDMA figures
tk1 in the MDMA figures equals (tk – 2*T).
ATA
tn, tj
—
lists the timing parameters for UDMA in burst.
shows timing when the UDMA in transfer starts,
Figure 68
Figure 69
Parameter from
tkjn
ton
toff
Table 71. MDMA Read and Write Timing Parameters (continued)
(Read),
(Write)
(Figure 68
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Figure 72
Figure 70. UDMA in Transfer Starts Timing Diagram
tn= tj= tkjn = time_jn * T – (tskew1 + tskew2 + tskew6)
ton = time_on
toff = time_off
and
shows timing when the UDMA in device terminates transfer, and
Figure
×
×
69) equals (tk – 2*T).
T – tskew1
T – tskew1
Value
Figure 71
shows timing when the UDMA in
Freescale Semiconductor
Controlling
Variable
time_jn
—
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