MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 15

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor
Temperature
Mnemonic
Monitor
UART-1
UART-2
UART-3
UART-4
UART-5
Block
IPTP
TZIC
USB
TVE
IEEE1588
Precision Time
Protocol
TV Encoder
TrustZone Aware
Interrupt
Controller
UART Interface
USB Controller
(Part of SATA
Block Name
Block)
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Table 2. i.MX53xD Digital and Analog Blocks (continued)
Connectivity
Peripherals
System
Control
Peripherals
Multimedia
ARM/Control
Connectivity
Peripherals
Connectivity
Peripherals
Subsystem
The IEEE 1588-2002 (version 1) standard defines a precision time protocol
(PTP) - which is a time-transfer protocol that enables synchronization of
networks (for example, Ethernet), to a high degree of accuracy and
precision.
The IEEE1588 hardware assist is composed of the two blocks: time stamp
unit and real time clock, which provide the timestamping protocol’s
functionality, generating and reading the needed timestamps.
The hardware-assisted implementation delivers more precise clock
synchronization at significantly lower CPU load compared to purely
software implementations.
The temperature sensor is an internal module to the i.MX53xD that
monitors the die temperature. The monitor is capable in generating SW
interrupt, or trigger the CCM, to reduce the core operating frequency.
The TV encoder, version 2.1 is implemented in conjunction with the image
processing unit (IPU) allowing handheld devices to display captured still
images and video directly on a TV or LCD projector. It supports composite
PAL/NTSC, VGA, S-video, and component up to HD1080p analog video
outputs.
The TrustZone interrupt controller (TZIC) collects interrupt requests from all
i.MX53xD sources and routes them to the ARM core. Each interrupt can be
configured as a normal or a secure interrupt. Software Force Registers and
software Priority Masking are also supported.
Each of the UART blocks supports the following serial data transmit/receive
protocols and configurations:
USB supports USB2.0 480 MHz, and contains:
The high-speed OTG module, which is internally connected to the HS USB
PHY, is equipped with transceiver-less logic to enable on-board USB
connectivity without USB transceivers
All the USB ports are equipped with standard digital interfaces (ULPI, HS
IC-USB) and transceiver-less logic to enable onboard USB connectivity
without USB transceivers.
• 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd,
• Programmable bit-rates up to 4 Mbps. This is a higher max baud rate
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
• One high-speed OTG sub-block with integrated HS USB PHY
• One high-speed host sub-block with integrated HS USB PHY
• Two identical high-speed Host modules
or none)
relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F
standard.
Brief Description
Modules List
15