MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 87
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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4.7.8.6
4.7.8.6.1
The IPU uses four control signals and data to operate a standard synchronous interface:
All synchronous display controls are generated on the base of an internally generated “local start point”.
The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.
The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved
relative to the local start point.
4.7.8.6.2
Figure 45
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
VSYNC
HSYNC
IPP_DISP_CLK
HSYNC
DRDY
IPP_DISP_CLK—Clock to display
HSYNC—Horizontal synchronization
VSYNC—Vertical synchronization
DRDY—Active data
DI_CLK internal DI clock, used for calculation of other controls.
IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is
selected). In active mode, IPP_DISP_CLK runs continuously.
HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.)
VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPP_PIN_3 is used as VSYNC.)
DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
IPP_DATA
depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure
Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
IPU Display Operating Signals
LCD Interface Functional Description
Figure 45. Interface Timing Diagram for TFT (Active Matrix) Panels
i.MX53xD Applications Processors for Consumer Products, Rev. 1
LINE 1
1
LINE 2
2
LINE 3
3
LINE 4
LINE n-1
m–1
Electrical Characteristics
LINE n
m
87
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