MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 112
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Electrical Characteristics
4.7.11
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
pin.
Figure 64
4.7.12
This section describes the timing parameters of the Parallel ATA module which are compliant with
ATA/ATAPI-6 specification.
Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode
has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA
module interface consist of a total of 29 pins. Some pins act on different function in different transfer
mode. There are different requirements of timing relationships among the function pins conform with
ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.
Table 67
modes.
112
1
CL of PWMO = 30 pF
Ref. No.
2a
2b
3a
3b
4a
4b
1
and
depicts the timing of the PWM, and
Pulse Width Modulator (PWM) Timing Parameters
PATA Timing Parameters
System CLK frequency
Clock high time
Clock low time
Clock fall time
Clock rise time
Output delay time
Output setup time
Figure 65
System Clock
PWM Output
i.MX53xD Applications Processors for Consumer Products, Rev. 1
define the AC characteristics of all the PATA interface signals in all data transfer
Parameter
Table 66. PWM Output Timing Parameter
1
Figure 64. PWM Timing
2a
4a
Table 66
2b
lists the PWM timing parameters.
12.29
9.91
8.71
Min
—
—
—
0
1
3a
3b
ipg_clk
4b
Max
9.37
0.5
0.5
—
—
—
Freescale Semiconductor
MHz
Unit
ns
ns
ns
ns
ns
ns
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