MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 53
![KIT DEVELOPMENT I.MX53](/photos/39/51/395134/4751369_sml.jpg)
MCIMX53-START
Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets
1.MCIMX53-START.pdf
(2 pages)
2.MCIMX53-START.pdf
(180 pages)
3.MCIMX53-START.pdf
(204 pages)
Specifications of MCIMX53-START
Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (2Mb)
4.6.6.3
Figure
signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge
according to corresponding assertion/negation control fields.
Freescale Semiconductor
,
WE1 BCLK Cycle time
WE2 BCLK Low Level
ID
16,
Width
Figure
Parameter
General EIM Timing-Synchronous Mode
17, and
Output Data
Address
2
i.MX53xD Applications Processors for Consumer Products, Rev. 1
CSx_B
ADV_B
Input Data
BCLK
BEy_B
WE_B
OE_B
WAIT_B
Table 38
0.4*t
Min
BCLK
t
BCD = 0
Figure 16. EIM Outputs Timing Diagram
Table 38. EIM Bus Timing Parameters
Figure 17. EIM Inputs Timing Diagram
specify the timings related to the EIM module. All EIM output control
WE10
WE14
WE16
WE12
WE8
WE4
WE6
WE20
WE18
Max
WE2
0.8*t
Min
2*t
WE1
BCD = 1
WE19
WE21
Max
...
WE3
1.2*t
Min
3*t
1
BCD = 2
Max
WE5
WE7
WE11
WE15
WE13
WE17
WE9
Electrical Characteristics
1.6*t
Min
4*t
BCD = 3
Max
53
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