IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 61

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

5.1
ISTER
select the test to be executed or the data register to be accessed or both.
68
Table-68 Instruction Register Description
5.2
5.2.1
the device revision, which can be used to verify the proper version or re-
vision number that has been used in the system under test. The IDR is
32 bits long and is partitioned as in Table-69. Data from the IDR is shifted
out to TDO LSB first.
Table-69 Device Identification Register Description
IEEE STD 1149.1 JTAG TEST ACCESS PORT
IDT82P5088
The IDR can be set to define the producer number, part number and
for details of the codes and the instructions related.
The IR (Instruction Register) with instruction decode block is used to
The instructions are shifted in LSB first to this 3-bit register. See
IR CODE
Bit No.
12-27
28-31
1-11
JTAG INSTRUCTIONS AND INSTRUCTION REG-
000
100
JTAG DATA REGISTER
DEVICE IDENTIFICATION REGISTER (IDR)
110
111
0
Sample / Preload The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed
INSTRUCTION
Bypass
Idcode
Extest
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the
EXTEST instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sam-
pled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting
the boundary scan register using the Shift-DR state. The signal on the output pins can be controlled by loading patterns
shifted in through input TDI into the boundary scan register using the Update-DR state.
between TDI and TDO. The normal path between IDT82P5088 logic and the I/O pins is maintained. Primary device inputs
and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can
then be viewed by shifting the boundary scan register using the Shift-DR state.
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification
code can then be shifted out using the Shift-DR state.
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to
bypass the device.
Producer Number
Device Revision
Comments
Part Number
Set to ‘1’
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
Table-
61
5.2.2
TDI input and TDO output, bypassing the BSR to reduce test access times.
5.2.3
digital I/O pins. The BSR is a 98 bits long shift register and is initialized and
read using the instruction EXTEST or SAMPLE/PRELOAD. Each pin is
related to one or more bits in the BSR. For details, please refer to the BSDL
file.
The BR consists of a single bit. It can provide a serial path between the
The BSR can apply and read test patterns in parallel to or from all the
BYPASS REGISTER (BR)
BOUNDARY SCAN REGISTER (BSR)
COMMENTS
February 5, 2009