IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 12

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IDT82P5088BBG

Manufacturer Part Number
IDT82P5088BBG
Description
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82P5088BBG

Includes
Integrated Clock Adapter
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Power (watts)
2.57W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-

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Table-1 Pin Description (Continued)
CLK_GEN_1.54
CLK_GEN_2.04
PIN DESCRIPTION
IDT82P5088
CLK_SEL[0]
CLK_SEL[1]
CLK_SEL[2]
REFA_OUT
REFB_OUT
RESET
GPIO0
GPIO1
OSCO
Name
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
LOS8
OSCI
4
8
Output /
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Type
PBGA256
Pin No.
B13
C13
D15
C14
B15
A16
D14
A15
B14
A14
E13
D13
R6
N6
M5
R4
N4
R3
T5
P5
LOSn: Loss of Signal Output for Channel 1~8
These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of
received signals in channel n. The LOSn pin will become low automatically when valid received signal is detected
again. The criteria of loss of signal are described in
OSCI: Crystal Oscillator Input
This pin is connected to an external clock source.
The clock frequency of OSCI is defined by CLK_SEL[2:0]. The clock accuracy should be ±32 ppm and duty cycle
should be from 40% to 60%.
OSCO: Crystal Oscillator Output
This pin outputs the inverted, buffered clock input from OSCI.
CLK_SEL[2:0]: Clock Selection
These three pins select the input clock signal:
When the CLK_SEL[2] pin is low, the input clock signal is N X 1.544 MHz;
When the CLK_SEL[2] pin is high, the input clock signal is N X 2.048 MHz.
When the CLK_SEL[1:0] pins are ‘00’, the N is 1;
When the CLK_SEL[1:0] pins are ‘01’, the N is 2;
When the CLK_SEL[1:0] pins are ‘10’, the N is 3;
When the CLK_SEL[1:0] pins are ‘11’, the N is 4.
CLK_SEL[2:0] are Schmitt-trigger inputs.
CLK_GEN_1.544: Clock Generator 1.544 MHz Output
This pin outputs the 1.544 MHz clock signal generated by the Clock Generator.
CLK_GEN_2.048: Clock Generator 2.048 MHz Output
This pin outputs the 2.048 MHz clock signal generated by the Clock Generator.
REFA_OUT: Reference Clock Output A
The frequecy is 2.048 MHz (E1) or 1.544 MHz (T1/J1)
When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of one
of the eight links. The link is selected by the RO1[2:0] bits (REFOUT, 07H).
When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (REFC, 3EH...).
Note: MCLK is a clock derived from OSCI using an internal PLL, and the frequency is 2.048 MHz (E1) or 1.544 MHz
(T1/J1).
REFB_OUT: Reference Clock Output B
The frequecy is 2.048 MHz (E1) or 1.544 MHz (T1/J1)
When no LOS is detected, this pin outputs a recovered clock from the Clock and Data Recovery function block of one
of the eight links. The link is selected by the RO2[2:0] bits (REFOUT, 07H).
When LOS is detected, this pin outputs MCLK or high level, as selected by the REFH_LOS bit (REFC, 3EH...).
RESET: Reset (Active Low)
A low pulse for more than 100 ns on this pin resets the device. All the registers are accessible 2 ms after the reset.
The RESET pin is a Schmitt-trigger input with a weak pull-up resistor. The OSCI clock must exist when the device is
reset.
General Purpose I/O [1:0]
These two pins can be defined as input pins or output pins by the DIR[1:0] bits (GPIO, 06H) respectively. When the
pins are input, their polarities are indicated by the LEVEL[1:0] bits (GPIO, 06H) respectively. When the pins are out-
put, their polarities are controlled by the LEVEL[1:0] bits (GPIO, 06H) respectively.
GPIO[1:0] are Schmitt-trigger input/output with a pull-up resistor.
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
Clock Generator
Control Interface
12
3.3.12 LOS AND AIS
Description
DETECTION.
February 5, 2009

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