IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 27

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IDT82P5088BBG

Manufacturer Part Number
IDT82P5088BBG
Description
IC LIU T1/E1/J1 OCTAL 256PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT82P5088BBG

Includes
Integrated Clock Adapter
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
8
Voltage - Supply
1.8V, 3.3V
Power (watts)
2.57W
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-

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RJA_IS bit (INTS1, 3BH...). When the RJA_IS bit is ‘1’, an interrupt will
be reported on the INT pin if enabled by the RJA_IE bit (INTENC1,
34H...).
by setting the RJA_LIMT bit (RJACF, 27H...). When the JA-Limit func-
tion is enabled, the speed of the outgoing data will be adjusted automat-
ically if the FIFO is close to its full or emptiness. The criteria of speed
adjustment start are listed in Table 17. Though the JA-Limit function can
reduce the possibility of FIFO overflow and underflow, the quality of jitter
attenuation is deteriorated.
Table-17 Criteria Of Speed Adjustment Start
interval between the read and write pointer of the FIFO or the peak-peak
interval between the read and write pointer of the FIFO can be indicated
in the RJITT[6:0] bits (RJITT, 39H...). When the RJITT_TEST bit is ‘0’,
the current interval between the read and write pointer of the FIFO will
be written into the RJITT[6:0] bits. When the RJITT_TEST bit is ‘1’, the
current interval will be compared with the old one in the RJITT[6:0] bits
and the larger one will be indicated by the RJITT[6:0] bits.
G.703, G.736 - 739, G.823, G.824, ETSI 300011, ETSI TBR 12/13,
AT&T TR62411, TR43802, TR-TSY 009, TR-TSY 253, TR-TRY 499
standards. Refer to Chapter 7.10 Jitter Tolerance and Chapter 7.11 Jitter
Transfer for details.
Table-18 Related Bit / Register In Chapter 3.3.11
FUNCTIONAL DESCRIPTION
IDT82P5088
RJA_DP[1:0]
RJITT_TEST
RJA_LIMT
RJITT[6:0]
RJA_BW
To avoid overflow or underflow, the JA-Limit function can be enabled
Selected by the RJITT_TEST bit (RJACF, 27H...), the real time
The performance of Receive Jitter Attenuator meets the ITU-T I.431,
RJA_IS
RJA_IE
RJA_E
FIFO Depth
Bit
128 bits
32 bits
64 bits
Receive Jitter Measure Value Indication
Receive Jitter Attenuation Configura-
Interrupt Enable Control 1
Interrupt Status 1
Register
Criteria Of Speed Adjustment Start
tion
2-bit close to full or empty
3-bit close to full or empty
4-bit close to full or empty
Address (Hex)
X3BH
X27H
X34H
X39H
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
27
3.3.12 LOS AND AIS DETECTION
3.3.12.1LOS DETECTION
nal level and pulse density of the received signal on RTIPn and RRINGn.
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT1, 2CH...). LOS will be
declared by pulling LOSn pin to high (LOS=1) and LOS interrupt will be gen-
erated if it is not masked.
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% for M consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT1,
2CH...). LOS status is cleared by pulling LOSn pin to low.
while P=Q+200 mVpp (200 mVpp is the LOS level detect hysteresis). In line
monitor mode, the amplitude threshold Q is fixed on 1600 mVpp, while
P=Q+400 mVpp (400 mVpp is the LOS level detect hysteresis).
(RCF1, 29H...), while P=Q+4 dB (4 dB is the LOS level detect hysteresis).
The LOS[4:0] default value is 10101 (-46 dB).
G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected
by LAC bit (MAINT1, 2CH...) and TE_MODE bit (T1E1 mode, 20H...).
both short haul and long haul application.
tion” at the RTIPn/RRINGn side and output recovery clock (but the quality
of the output clock can not be guaranteed when the input level is lower than
The Loss of Signal Detector monitors the amplitude of the incoming sig-
• LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
• LOS clear (LOS=0)
The LOS is cleared when the incoming signal has “transitions”, i.e.,
• LOS detect level threshold
• Criteria for declare and clear of a LOS detect
The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and
Table-19
• All Ones output during LOS
On the system side, the RDPn/RDNn will reflect the input pulse “transi-
(observing windows= M)
In short haul mode, the amplitude threshold Q is fixed on 800 mVpp,
In long haul mode, the value of Q can be selected by LOS[4:0] bit
density=OK
signal level>P
and
Figure-13 LOS Declare and Clear
Table-20
summarize LOS declare and clear criteria for
LOS=1
LOS=0
(observing windows= N)
signal level<Q
February 5, 2009

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