IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 35

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

received errors when the CNT_MD bit (MAINT6, 31H...) is set to ‘0’. When
there is a ‘0’ to ‘1’ transition on the CNT_STOP bit (MAINT6, 31H...), the
data in the counter will be transferred to (CNTL, 3CH...) and (CNTH,
3DH...), then the counter will be reset. The errors occurred during the trans-
fer will be accumulated to the next round. If the counter overflows, a counter
overflow interrupt indicated by CNTOV_IS bit (INTS1, 3BH...) will be gen-
erated if it is not masked by CNT_IE bit (INTENC1, 34H...).
Note: 1. It is recommended that users should do the followings within next round
FUNCTIONAL DESCRIPTION
IDT82P5088
• Manual Report Mode
In Manual Report Mode, the internal Error Counter starts to count the
of error counting: Read the data in CNTL and CNTH; Reset CNT_TRF
bit for the next ‘0’ to ‘1’ transition on this bit.
Figure-18 Manual Report Mode
N
Reset CNT_STOP for the
CNTL, CNTH
counter
counter
CNTH within next round
Read the data in CNTL,
Manual Report mode
next '0' to '1' transition
A '0' to '1' transition
on CNT_STOP?
(CNT_MD=0)
counting
0
Y
data in
1
same process
next round
repeat the
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
35
3.6.3
stream, will a ‘0’ to ‘1’ transition on the BPV_INS bit (MAINT6, 31H...) gen-
erate a bipolar violation pulse, and the polarity of the second ‘1’ in the series
will be inverted.
a logic error during the PRBS/QRSS transmission.
3.7
DFM_OFF bit (TCF1, 23H...). If the transmit driver failure monitor is
enabled, the transmit driver failure will be captured by DF_S bit (STAT0,
36H...). The transition of the DF_S bit is reflected by DF_IS bit (INTS0,
3AH...), and, if enabled by DF_IE bit (INTENC0, 33H...), will generate an
interrupt. When there is a short circuit on the TTIPn/TRINGn port, the output
current will be limited to 100 mA (typical) and an interrupt will be generated.
Only when three consecutive ‘1’s are detected in the transmit data
A ‘0’ to ‘1’ transition on the EER_INS bit (MAINT6, 31H...) will generate
The transmit driver failure monitor can be enabled or disabled by setting
LINE DRIVER FAILURE MONITORING
BIPOLAR VIOLATION AND PRBS ERROR INSERTION
February 5, 2009