IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 30

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

Table-21 AIS Condition
3.4
Activate/Deactivate Loopback Code) will be generated and detected by the
IDT82P5088. TCLKn is used as the reference clock by default. MCLK can
also be used as the reference clock by setting the PATT_CLK bit (MAINT1,
2CH...) to ‘1’.
(MAINT1, 2CH...) are set to ‘00’, the transmit path will operate in normal
mode.
3.4.1
stream when the PATT[1:0] bits (MAINT1, 2CH...) are set to ‘01’. The trans-
mit data stream is output from TTIPn/TRINGn. In this case, either TCLKn
or MCLK can be used as the transmit clock, as selected by the PATT_CLK
bit (MAINT1, 2CH...).
3.4.2
inserted into the transmit data stream when the PATT[1:0] bits (MAINT1,
2CH...) are set to ‘00’.
3.4.3
in the receive direction by IDT82P5088. The QRSS is 2
cations and the PRBS is 2
restrictions according to the AT&T TR62411 and ITU-T O.151.
FUNCTIONAL DESCRIPTION
IDT82P5088
detected
cleared
The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and
If the PATT_CLK bit (MAINT1, 2CH...) is set to ‘0’ and the PATT[1:0] bits
In transmit direction, the All Ones data can be inserted into the data
If the PATT_CLK bit (MAINT1, 2CH...) is set to ‘1’, the All Zeros will be
A PRBS/QRSS will be generated in the transmit direction and detected
AIS
AIS
TRANSMIT AND DETECT INTERNAL PATTERNS
TRANSMIT ALL ONES
TRANSMIT ALL ZEROS
PRBS/QRSS GENERATION AND DETECTION
Less than 3 zeros contained in each of two consecutive
512-bit streams are received
3 or more zeros contained in each of two consecutive
512-bit streams are received
(LAC bit is set to ‘0’ by default)
15
-1 for E1 applications, with maximum zero
ITU G.775 for E1
20
-1 for T1/J1 appli-
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
Less than 3 zeros contained in a 512-bit
stream are received
3 or more zeros contained in a 512-bit
stream are received
(LAC bit is set to ‘1’)
ETSI 300233 for E1
30
QRSS pattern will be inserted into the transmit data stream with the MSB
first. The PRBS/QRSS pattern will be transmitted directly or invertedly.
PRBS/QRSS has reached synchronization status, the PRBS_S bit
(STAT0, 36H...) will be set to ‘1’, even in the presence of a logic error rate
less than or equal to 10
are shown in Table-22.
Table-22 Criteria for Setting/Clearing the PRBS_S Bit
2CH...).
3AH...). The PRBS_IES bit (INTES, 35H...) can be used to determine
whether the ‘0’ to ‘1’ change of PRBS_S bit will be captured by the PRBS_IS
bit or any changes of PRBS_S bit will be captured by the PRBS_IS bit. When
the PRBS_IS bit is ‘1’, an interrupt will be generated if the PRBS_IE bit
(INTENC0, 33H...) is set to ‘1’.
counter if the ERR_SEL [1:0] bits (MAINT6, 31H...) are set to ‘00’. Refer to
Refer to
operation of the error counter.
PRBS/QRSS
Detection
PRBS/QRSS
Missing
When the PATT[1:0] bits (MAINT1, 2CH...) are set to ‘10’, the PRBS/
The PRBS/QRSS in the received data stream will be monitored. If the
PRBS data can be inverted through setting the PRBS_INV bit (MAINT1,
Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0,
The received PRBS/QRSS logic errors can be counted in a 16-bit
3.6 ERROR DETECTION/COUNTING AND INSERTION
6 or less than 6 bit errors detected in a 64 bits hopping window.
More than 6 bit errors detected in a 64 bits hopping window.
-1
. The criteria for setting/clearing the PRBS_S bit
Less than 9 zeros contained in an 8192-bit stream
(a ones density of 99.9% over a period of 5.3ms)
9 or more zeros contained in an 8192-bit stream
are received
ANSI T1.231 for T1/J1
February 5, 2009
for the