IDT82P5088BBG IDT, Integrated Device Technology Inc, IDT82P5088BBG Datasheet - Page 36

• Manufacturer Part Number: IDT82P5088BBG
• Description: IC LIU T1/E1/J1 OCTAL 256PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P5088BBG

• Includes: Integrated Clock Adapter
• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 8
• Voltage - Supply: 1.8V, 3.3V
• Power (watts): 2.57W
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 256-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -

3.8
3.8.1
E1 Rate of Transmit System interface, this clock must keep the Crystal
Oscillator same with system transmit clock (TSCKn/MTSCK).
Table-24.
Table-24 Reference Clock Selection
FUNCTIONAL DESCRIPTION
IDT82P5088
The OSCI pin is connected to an external Crystal Oscillator. In T1 mode
The OSCO pin outputs the inverted, buffered clock input from OSCI.
The clock frequency of OSCI is defined by CLK_SEL[2:0]. Refer to
Oscillator
Crystal
CLK_SEL[2:0]
CLOCK GENERATOR AND TCLK
CLOCK GENERATOR
CLK_SEL[2:0]
normal operation mode
OSCO
000
001
010
011
100
101
110
111
Figure-19 Clock Generator
OSCI
clocked
Clock Generator
Input Clock Signal (MHz)
TCLKn status?
1 X 1.544
2 X 1.544
3 X 1.544
4 X 1.544
1 X 2.048
2 X 2.048
3 X 2.048
4 X 2.048
Figure-20 TCLK Operation Flowchart
CLK_GEN_1.544
CLK_GEN_2.048
REFA_OUT
REFB_OUT
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
generates transmit clock loss
transmitter n enters high
interrupt if not masked
impedance status and
L/H
36
CLK_GEN_2.048 outputs the 2.048 MHz clock signal.
or 1.544 MHz (T1/J1). When no LOS is detected, the REFA_OUT/
REFB_OUT pins output a recovered clock from the Clock and Data Recov-
ery function block of one of the eight links. The REFA_OUT link is selected
by the RO1[2:0] bits (b2~0, T1/J1-007H / b2~0, E1-007H); The REFB_OUT
link is selected by the RO2[2:0] bits (b5~3, T1/J1-007H / b5~3, E1-007H).
When LOS is detected, the REFA_OUT/REFB_OUT pins output MCLK or
high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH,... / b0, E1-
03EH,...). *
frequency is 2.048 MHz (E1) or 1.544 MHz (T1/J1).
3.8.2
The active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0,
22H...). During Transmit All Ones, PRBS/QRSS patterns or Inband Loop-
back Code, either TCLKn or MCLK can be used as the reference clock. This
is selected by the PATT_CLK bit (MAINT1, 2CH...).
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT1, 2CH) is set to ‘1’. In AIS condi-
tion, the RAISE bit (MAINT1, 2CH) is set to ‘1’.
bit (STAT0, 36H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
is not using MCLK to transmit internal patterns (TAOS, All Zeros, PRBS and
in-band loopback code). When TCLKn is detected again, TCLK_LOS bit
(STAT0, 36H...) will be cleared. The reference frequency to detect a TCLKn
loss is derived from MCLK.
clocked
The CLK_GEN_1.544 pin outputs the 1.544 MHz clock signal and the
The frequecy of the REFA_OUT/REFB_OUT pins is 2.048 MHz (E1)
Note: MCLK is a clock derived from OSCI using an internal PLL, and the
The TCLKn is used to sample the transmit data on TDn/TDPn, TDNn.
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
TRANSMIT CLOCK (TCLK)
all transmitters high
impedance status
MCLK=H/L?
yes
February 5, 2009